[#ftl] [#list configs as dt] [#assign data = dt] [#assign peripheralParams =dt.peripheralParams] [#assign peripheralGPIOParams =dt.peripheralGPIOParams] [#assign usedIPs =dt.usedIPs]GPIOPorts [#assign GPIOs =dt.GPIOPorts] /* ----------------------------------------------------------------------------- * Copyright (C) 2014 ARM Limited. All rights reserved. * * $Date: 4. February 2014 * $Revision: V1.03 * * Project: RTE Device Configuration for ST STM32F4xx * -------------------------------------------------------------------------- */ //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H [#assign i =0] #define GPIO_PORT(num) \ [#list GPIOs as gpio] ((num == ${i}) ? ${gpio?replace("P","GPIO")} : \ [#assign i =i+1] [/#list] NULL) // Clock Configuration // High-speed Internal Clock <1-999999999> #define RTE_HSI [#if peripheralParams.get("RCC")?? && peripheralParams.get("RCC").get("HSI_VALUE")??]${peripheralParams.get("RCC").get("HSI_VALUE")}[/#if] // High-speed External Clock <1-999999999> #define RTE_HSE ${peripheralParams.get("RCC").get("HSE_VALUE")} // System Clock <1-999999999> #define RTE_SYSCLK ${peripheralParams.get("RCC").get("SYSCLKFreq_VALUE")} // AHB Clock <1-999999999> #define RTE_HCLK 168000000 // APB1 Clock <1-999999999> #define RTE_PCLK1 42000000 // APB2 Clock <1-999999999> #define RTE_PCLK2 84000000 // 48MHz Clock #define RTE_PLL48CK 48000000 // // USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_UART1] // Configuration settings for Driver_UART1 in component ::Drivers:UART #define RTE_USART1 0 // USART1_TX Pin <0=>PA9 <1=>PB6 #define RTE_USART1_TX_ID 0 #if (RTE_USART1_TX_ID == 0) #define RTE_USART1_TX_PORT GPIOA #define RTE_USART1_TX_BIT 9 #elif (RTE_USART1_TX_ID == 1) #define RTE_USART1_TX_PORT GPIOB #define RTE_USART1_TX_BIT 6 #else #error "Invalid USART1_TX Pin Configuration!" #endif // USART1_RX Pin <0=>PA10 <1=>PB7 #define RTE_USART1_RX_ID 0 #if (RTE_USART1_RX_ID == 0) #define RTE_USART1_RX_PORT GPIOA #define RTE_USART1_RX_BIT 10 #elif (RTE_USART1_RX_ID == 1) #define RTE_USART1_RX_PORT GPIOB #define RTE_USART1_RX_BIT 7 #else #error "Invalid USART1_RX Pin Configuration!" #endif // Synchronous // USART1_CK Pin <0=>PA8 // #define RTE_USART1_CK 0 #define RTE_USART1_CK_ID 0 #if (RTE_USART1_CK_ID == 0) #define RTE_USART1_CK_PORT GPIOA #define RTE_USART1_CK_BIT 8 #else #error "Invalid USART1_CK Pin Configuration!" #endif // Hardware flow control // USART1_CTS Pin <0=>PA11 // USART1_RTS Pin <0=>PA12 // Manual CTS/RTS // #define RTE_USART1_HW_FLOW 0 #define RTE_USART1_CTS_ID 0 #define RTE_USART1_RTS_ID 0 #define RTE_USART1_MANUAL_FLOW 0 #if (RTE_USART1_CTS_ID == 0) #define RTE_USART1_CTS_PORT GPIOA #define RTE_USART1_CTS_BIT 11 #else #error "Invalid USART1_CTS Pin Configuration!" #endif #if (RTE_USART1_RTS_ID == 0) #define RTE_USART1_RTS_PORT GPIOA #define RTE_USART1_RTS_BIT 12 #else #error "Invalid USART1_RTS Pin Configuration!" #endif // DMA Rx // Number <2=>2 // Selects DMA Number (only DMA2 can be used) // Stream <2=>2 <5=>5 // Selects DMA Stream (only Stream 2 or 5 can be used) // Channel <4=>4 // Selects DMA Channel (only Channel 4 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_USART1_RX_DMA 1 #define RTE_USART1_RX_DMA_NUMBER 2 #define RTE_USART1_RX_DMA_STREAM 2 #define RTE_USART1_RX_DMA_CHANNEL 4 #define RTE_USART1_RX_DMA_PRIORITY 0 // DMA Tx // Number <2=>2 // Selects DMA Number (only DMA2 can be used) // Stream <7=>7 // Selects DMA Stream (only Stream 7 can be used) // Channel <4=>4 // Selects DMA Channel (only Channel 4 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_USART1_TX_DMA 1 #define RTE_USART1_TX_DMA_NUMBER 2 #define RTE_USART1_TX_DMA_STREAM 7 #define RTE_USART1_TX_DMA_CHANNEL 4 #define RTE_USART1_TX_DMA_PRIORITY 0 // // USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_UART2] // Configuration settings for Driver_UART2 in component ::Drivers:UART #define RTE_USART2 0 // USART2_TX Pin <0=>PA2 <1=>PD5 #define RTE_USART2_TX_ID 0 #if (RTE_USART2_TX_ID == 0) #define RTE_USART2_TX_PORT GPIOA #define RTE_USART2_TX_BIT 2 #elif (RTE_USART2_TX_ID == 1) #define RTE_USART2_TX_PORT GPIOD #define RTE_USART2_TX_BIT 5 #else #error "Invalid USART2_TX Pin Configuration!" #endif // USART2_RX Pin <0=>PA3 <1=>PD6 #define RTE_USART2_RX_ID 0 #if (RTE_USART2_RX_ID == 0) #define RTE_USART2_RX_PORT GPIOA #define RTE_USART2_RX_BIT 3 #elif (RTE_USART2_RX_ID == 1) #define RTE_USART2_RX_PORT GPIOD #define RTE_USART2_RX_BIT 6 #else #error "Invalid USART2_RX Pin Configuration!" #endif // Synchronous // USART2_CK Pin <0=>PA4 <1=>PD7 // #define RTE_USART2_CK 0 #define RTE_USART2_CK_ID 0 #if (RTE_USART2_CK_ID == 0) #define RTE_USART2_CK_PORT GPIOA #define RTE_USART2_CK_BIT 4 #elif (RTE_USART2_CK_ID == 1) #define RTE_USART2_CK_PORT GPIOD #define RTE_USART2_CK_BIT 7 #else #error "Invalid USART2_CK Pin Configuration!" #endif // Hardware flow control // USART2_CTS Pin <0=>PA0 <1=>PD3 // USART2_RTS Pin <0=>PA1 <1=>PD4 // Manual CTS/RTS // #define RTE_USART2_HW_FLOW 0 #define RTE_USART2_CTS_ID 0 #define RTE_USART2_RTS_ID 0 #define RTE_USART2_MANUAL_FLOW 0 #if (RTE_USART2_CTS_ID == 0) #define RTE_USART2_CTS_PORT GPIOA #define RTE_USART2_CTS_BIT 0 #elif (RTE_USART2_CTS_ID == 1) #define RTE_USART2_CTS_PORT GPIOD #define RTE_USART2_CTS_BIT 3 #else #error "Invalid USART2_CTS Pin Configuration!" #endif #if (RTE_USART2_RTS_ID == 0) #define RTE_USART2_RTS_PORT GPIOA #define RTE_USART2_RTS_BIT 1 #elif (RTE_USART2_RTS_ID == 1) #define RTE_USART2_RTS_PORT GPIOD #define RTE_USART2_RTS_BIT 4 #else #error "Invalid USART2_RTS Pin Configuration!" #endif // DMA Rx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <5=>5 // Selects DMA Stream (only Stream 5 can be used) // Channel <4=>4 // Selects DMA Channel (only Channel 4 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_USART2_RX_DMA 1 #define RTE_USART2_RX_DMA_NUMBER 1 #define RTE_USART2_RX_DMA_STREAM 5 #define RTE_USART2_RX_DMA_CHANNEL 4 #define RTE_USART2_RX_DMA_PRIORITY 0 // DMA Tx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <6=>6 // Selects DMA Stream (only Stream 6 can be used) // Channel <4=>4 // Selects DMA Channel (only Channel 4 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_USART2_TX_DMA 1 #define RTE_USART2_TX_DMA_NUMBER 1 #define RTE_USART2_TX_DMA_STREAM 6 #define RTE_USART2_TX_DMA_CHANNEL 4 #define RTE_USART2_TX_DMA_PRIORITY 0 // // USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_UART3] // Configuration settings for Driver_UART3 in component ::Drivers:UART #define RTE_USART3 0 // USART3_TX Pin <0=>PB10 <1=>PC10 <2=>PD8 #define RTE_USART3_TX_ID 0 #if (RTE_USART3_TX_ID == 0) #define RTE_USART3_TX_PORT GPIOB #define RTE_USART3_TX_BIT 10 #elif (RTE_USART3_TX_ID == 1) #define RTE_USART3_TX_PORT GPIOC #define RTE_USART3_TX_BIT 10 #elif (RTE_USART3_TX_ID == 2) #define RTE_USART3_TX_PORT GPIOD #define RTE_USART3_TX_BIT 8 #else #error "Invalid USART3_TX Pin Configuration!" #endif // USART3_RX Pin <0=>PB11 <1=>PC11 <2=>PD9 #define RTE_USART3_RX_ID 0 #if (RTE_USART3_RX_ID == 0) #define RTE_USART3_RX_PORT GPIOB #define RTE_USART3_RX_BIT 11 #elif (RTE_USART3_RX_ID == 1) #define RTE_USART3_RX_PORT GPIOC #define RTE_USART3_RX_BIT 11 #elif (RTE_USART3_RX_ID == 2) #define RTE_USART3_RX_PORT GPIOD #define RTE_USART3_RX_BIT 9 #else #error "Invalid USART3_RX Pin Configuration!" #endif // Synchronous // USART3_CK Pin <0=>PB12 <1=>PC12 <2=>PD10 // #define RTE_USART3_CK 0 #define RTE_USART3_CK_ID 0 #if (RTE_USART3_CK_ID == 0) #define RTE_USART3_CK_PORT GPIOB #define RTE_USART3_CK_BIT 12 #elif (RTE_USART3_CK_ID == 1) #define RTE_USART3_CK_PORT GPIOC #define RTE_USART3_CK_BIT 12 #elif (RTE_USART3_CK_ID == 2) #define RTE_USART3_CK_PORT GPIOD #define RTE_USART3_CK_BIT 10 #else #error "Invalid USART3_CK Pin Configuration!" #endif // Hardware flow control // USART3_CTS Pin <0=>PB13 <1=>PD11 // USART3_RTS Pin <0=>PB14 <1=>PD12 // Manual CTS/RTS // #define RTE_USART3_HW_FLOW 0 #define RTE_USART3_CTS_ID 0 #define RTE_USART3_RTS_ID 0 #define RTE_USART3_MANUAL_FLOW 0 #if (RTE_USART3_CTS_ID == 0) #define RTE_USART3_CTS_PORT GPIOB #define RTE_USART3_CTS_BIT 13 #elif (RTE_USART3_CTS_ID == 1) #define RTE_USART3_CTS_PORT GPIOD #define RTE_USART3_CTS_BIT 11 #else #error "Invalid USART3_CTS Pin Configuration!" #endif #if (RTE_USART3_RTS_ID == 0) #define RTE_USART3_RTS_PORT GPIOB #define RTE_USART3_RTS_BIT 14 #elif (RTE_USART3_RTS_ID == 1) #define RTE_USART3_RTS_PORT GPIOD #define RTE_USART3_RTS_BIT 12 #else #error "Invalid USART3_RTS Pin Configuration!" #endif // DMA Rx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <1=>1 // Selects DMA Stream (only Stream 1 can be used) // Channel <4=>4 // Selects DMA Channel (only Channel 4 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_USART3_RX_DMA 1 #define RTE_USART3_RX_DMA_NUMBER 1 #define RTE_USART3_RX_DMA_STREAM 1 #define RTE_USART3_RX_DMA_CHANNEL 4 #define RTE_USART3_RX_DMA_PRIORITY 0 // DMA Tx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <3=>3 // Selects DMA Stream (only Stream 3 can be used) // Channel <4=>4 // Selects DMA Channel (only Channel 4 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_USART3_TX_DMA 1 #define RTE_USART3_TX_DMA_NUMBER 1 #define RTE_USART3_TX_DMA_STREAM 3 #define RTE_USART3_TX_DMA_CHANNEL 4 #define RTE_USART3_TX_DMA_PRIORITY 0 // // UART4 (Universal asynchronous receiver transmitter) [Driver_UART4] // Configuration settings for Driver_UART4 in component ::Drivers:UART #define RTE_UART4 0 // UART4_TX Pin <0=>PA0 <1=>PC10 #define RTE_UART4_TX_ID 0 #if (RTE_UART4_TX_ID == 0) #define RTE_UART4_TX_PORT GPIOA #define RTE_UART4_TX_BIT 0 #elif (RTE_UART4_TX_ID == 1) #define RTE_UART4_TX_PORT GPIOC #define RTE_UART4_TX_BIT 10 #else #error "Invalid UART4_TX Pin Configuration!" #endif // UART4_RX Pin <0=>PA1 <1=>PC11 #define RTE_UART4_RX_ID 0 #if (RTE_UART4_RX_ID == 0) #define RTE_UART4_RX_PORT GPIOA #define RTE_UART4_RX_BIT 1 #elif (RTE_UART4_RX_ID == 1) #define RTE_UART4_RX_PORT GPIOC #define RTE_UART4_RX_BIT 11 #else #error "Invalid UART4_RX Pin Configuration!" #endif // DMA Rx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <2=>2 // Selects DMA Stream (only Stream 2 can be used) // Channel <4=>4 // Selects DMA Channel (only Channel 4 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_UART4_RX_DMA 1 #define RTE_UART4_RX_DMA_NUMBER 1 #define RTE_UART4_RX_DMA_STREAM 2 #define RTE_UART4_RX_DMA_CHANNEL 4 #define RTE_UART4_RX_DMA_PRIORITY 0 // DMA Tx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <4=>4 // Selects DMA Stream (only Stream 4 can be used) // Channel <4=>4 // Selects DMA Channel (only Channel 4 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_UART4_TX_DMA 1 #define RTE_UART4_TX_DMA_NUMBER 1 #define RTE_UART4_TX_DMA_STREAM 4 #define RTE_UART4_TX_DMA_CHANNEL 4 #define RTE_UART4_TX_DMA_PRIORITY 0 // // UART5 (Universal asynchronous receiver transmitter) [Driver_UART5] // Configuration settings for Driver_UART5 in component ::Drivers:UART #define RTE_UART5 0 // UART5_TX Pin <0=>PC12 #define RTE_UART5_TX_ID 0 #if (RTE_UART5_TX_ID == 0) #define RTE_UART5_TX_PORT GPIOC #define RTE_UART5_TX_BIT 12 #else #error "Invalid UART5_TX Pin Configuration!" #endif // UART5_RX Pin <0=>PD2 #define RTE_UART5_RX_ID 0 #if (RTE_UART5_RX_ID == 0) #define RTE_UART5_RX_PORT GPIOD #define RTE_UART5_RX_BIT 2 #else #error "Invalid UART5_RX Pin Configuration!" #endif // DMA Rx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <0=>0 // Selects DMA Stream (only Stream 0 can be used) // Channel <4=>4 // Selects DMA Channel (only Channel 4 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_UART5_RX_DMA 1 #define RTE_UART5_RX_DMA_NUMBER 1 #define RTE_UART5_RX_DMA_STREAM 0 #define RTE_UART5_RX_DMA_CHANNEL 4 #define RTE_UART5_RX_DMA_PRIORITY 0 // DMA Tx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <7=>7 // Selects DMA Stream (only Stream 7 can be used) // Channel <4=>4 // Selects DMA Channel (only Channel 4 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_UART5_TX_DMA 1 #define RTE_UART5_TX_DMA_NUMBER 1 #define RTE_UART5_TX_DMA_STREAM 7 #define RTE_UART5_TX_DMA_CHANNEL 4 #define RTE_UART5_TX_DMA_PRIORITY 0 // // USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_UART6] // Configuration settings for Driver_UART6 in component ::Drivers:UART #define RTE_USART6 0 // USART6_TX Pin <0=>PC6 <1=>PG14 #define RTE_USART6_TX_ID 0 #if (RTE_USART6_TX_ID == 0) #define RTE_USART6_TX_PORT GPIOC #define RTE_USART6_TX_BIT 6 #elif (RTE_USART6_TX_ID == 1) #define RTE_USART6_TX_PORT GPIOG #define RTE_USART6_TX_BIT 14 #else #error "Invalid USART6_TX Pin Configuration!" #endif // USART6_RX Pin <0=>PC7 <1=>PG9 #define RTE_USART6_RX_ID 0 #if (RTE_USART6_RX_ID == 0) #define RTE_USART6_RX_PORT GPIOC #define RTE_USART6_RX_BIT 7 #elif (RTE_USART6_RX_ID == 1) #define RTE_USART6_RX_PORT GPIOG #define RTE_USART6_RX_BIT 9 #else #error "Invalid USART6_RX Pin Configuration!" #endif // Synchronous // USART6_CK Pin <0=>PC8 <1=>PG7 // #define RTE_USART6_CK 0 #define RTE_USART6_CK_ID 0 #if (RTE_USART6_CK_ID == 0) #define RTE_USART6_CK_PORT GPIOC #define RTE_USART6_CK_BIT 8 #elif (RTE_USART6_CK_ID == 1) #define RTE_USART6_CK_PORT GPIOG #define RTE_USART6_CK_BIT 7 #else #error "Invalid USART6_CK Pin Configuration!" #endif // Hardware flow control // USART6_CTS Pin <0=>PG13 <1=>PG15 // USART6_RTS Pin <0=>PG8 <1=>PG12 // Manual CTS/RTS // #define RTE_USART6_HW_FLOW 0 #define RTE_USART6_CTS_ID 0 #define RTE_USART6_RTS_ID 0 #define RTE_USART6_MANUAL_FLOW 0 #if (RTE_USART6_CTS_ID == 0) #define RTE_USART6_CTS_PORT GPIOG #define RTE_USART6_CTS_BIT 13 #elif (RTE_USART6_CTS_ID == 1) #define RTE_USART6_CTS_PORT GPIOG #define RTE_USART6_CTS_BIT 15 #else #error "Invalid USART6_CTS Pin Configuration!" #endif #if (RTE_USART6_RTS_ID == 0) #define RTE_USART6_RTS_PORT GPIOG #define RTE_USART6_RTS_BIT 8 #elif (RTE_USART6_RTS_ID == 1) #define RTE_USART6_RTS_PORT GPIOG #define RTE_USART6_RTS_BIT 12 #else #error "Invalid USART6_RTS Pin Configuration!" #endif // DMA Rx // Number <2=>2 // Selects DMA Number (only DMA2 can be used) // Stream <1=>1 <2=>2 // Selects DMA Stream (only Stream 1 or 2 can be used) // Channel <5=>5 // Selects DMA Channel (only Channel 5 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_USART6_RX_DMA 1 #define RTE_USART6_RX_DMA_NUMBER 2 #define RTE_USART6_RX_DMA_STREAM 1 #define RTE_USART6_RX_DMA_CHANNEL 5 #define RTE_USART6_RX_DMA_PRIORITY 0 // DMA Tx // Number <2=>2 // Selects DMA Number (only DMA2 can be used) // Stream <6=>6 <7=>7 // Selects DMA Stream (only Stream 6 or 7 can be used) // Channel <5=>5 // Selects DMA Channel (only Channel 5 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_USART6_TX_DMA 1 #define RTE_USART6_TX_DMA_NUMBER 2 #define RTE_USART6_TX_DMA_STREAM 6 #define RTE_USART6_TX_DMA_CHANNEL 5 #define RTE_USART6_TX_DMA_PRIORITY 0 // // I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] // Configuration settings for Driver_I2C1 in component ::Drivers:I2C #define RTE_I2C1 0 // I2C1_SCL Pin <0=>PB6 <1=>PB8 #define RTE_I2C1_SCL_PORT_ID 0 #if (RTE_I2C1_SCL_PORT_ID == 0) #define RTE_I2C1_SCL_PORT GPIOB #define RTE_I2C1_SCL_BIT 6 #elif (RTE_I2C1_SCL_PORT_ID == 1) #define RTE_I2C1_SCL_PORT GPIOB #define RTE_I2C1_SCL_BIT 8 #else #error "Invalid I2C1_SCL Pin Configuration!" #endif // I2C1_SDA Pin <0=>PB7 <1=>PB9 #define RTE_I2C1_SDA_PORT_ID 0 #if (RTE_I2C1_SDA_PORT_ID == 0) #define RTE_I2C1_SDA_PORT GPIOB #define RTE_I2C1_SDA_BIT 7 #elif (RTE_I2C1_SDA_PORT_ID == 1) #define RTE_I2C1_SDA_PORT GPIOB #define RTE_I2C1_SDA_BIT 9 #else #error "Invalid I2C1_SDA Pin Configuration!" #endif // DMA Rx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <0=>0 <5=>5 // Selects DMA Stream (only Stream 0 or 5 can be used) // Channel <1=>1 // Selects DMA Channel (only Channel 1 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_I2C1_RX_DMA 1 #define RTE_I2C1_RX_DMA_NUMBER 1 #define RTE_I2C1_RX_DMA_STREAM 0 #define RTE_I2C1_RX_DMA_CHANNEL 1 #define RTE_I2C1_RX_DMA_PRIORITY 0 // DMA Tx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <6=>6 <7=>7 // Selects DMA Stream (only Stream 6 or 7 can be used) // Channel <1=>1 // Selects DMA Channel (only Channel 1 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_I2C1_TX_DMA 1 #define RTE_I2C1_TX_DMA_NUMBER 1 #define RTE_I2C1_TX_DMA_STREAM 6 #define RTE_I2C1_TX_DMA_CHANNEL 1 #define RTE_I2C1_TX_DMA_PRIORITY 0 // // I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] // Configuration settings for Driver_I2C2 in component ::Drivers:I2C #define RTE_I2C2 0 // I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 #define RTE_I2C2_SCL_PORT_ID 0 #if (RTE_I2C2_SCL_PORT_ID == 0) #define RTE_I2C2_SCL_PORT GPIOF #define RTE_I2C2_SCL_BIT 1 #elif (RTE_I2C2_SCL_PORT_ID == 1) #define RTE_I2C2_SCL_PORT GPIOH #define RTE_I2C2_SCL_BIT 4 #elif (RTE_I2C2_SCL_PORT_ID == 2) #define RTE_I2C2_SCL_PORT GPIOB #define RTE_I2C2_SCL_BIT 10 #else #error "Invalid I2C2_SCL Pin Configuration!" #endif // I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 #define RTE_I2C2_SDA_PORT_ID 0 #if (RTE_I2C2_SDA_PORT_ID == 0) #define RTE_I2C2_SDA_PORT GPIOF #define RTE_I2C2_SDA_BIT 0 #elif (RTE_I2C2_SDA_PORT_ID == 1) #define RTE_I2C2_SDA_PORT GPIOH #define RTE_I2C2_SDA_BIT 5 #elif (RTE_I2C2_SDA_PORT_ID == 2) #define RTE_I2C2_SDA_PORT GPIOB #define RTE_I2C2_SDA_BIT 11 #else #error "Invalid I2C2_SCL Pin Configuration!" #endif // DMA Rx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <2=>2 <3=>3 // Selects DMA Stream (only Stream 2 or 3 can be used) // Channel <7=>7 // Selects DMA Channel (only Channel 7 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_I2C2_RX_DMA 1 #define RTE_I2C2_RX_DMA_NUMBER 1 #define RTE_I2C2_RX_DMA_STREAM 2 #define RTE_I2C2_RX_DMA_CHANNEL 7 #define RTE_I2C2_RX_DMA_PRIORITY 0 // DMA Tx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <7=>7 // Selects DMA Stream (only Stream 7 can be used) // Channel <7=>7 // Selects DMA Channel (only Channel 1 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_I2C2_TX_DMA 1 #define RTE_I2C2_TX_DMA_NUMBER 1 #define RTE_I2C2_TX_DMA_STREAM 7 #define RTE_I2C2_TX_DMA_CHANNEL 7 #define RTE_I2C2_TX_DMA_PRIORITY 0 // // I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] // Configuration settings for Driver_I2C3 in component ::Drivers:I2C #define RTE_I2C3 0 // I2C3_SCL Pin <0=>PH7 <1=>PA8 #define RTE_I2C3_SCL_PORT_ID 0 #if (RTE_I2C3_SCL_PORT_ID == 0) #define RTE_I2C3_SCL_PORT GPIOH #define RTE_I2C3_SCL_BIT 7 #elif (RTE_I2C3_SCL_PORT_ID == 1) #define RTE_I2C3_SCL_PORT GPIOA #define RTE_I2C3_SCL_BIT 8 #else #error "Invalid I2C3_SCL Pin Configuration!" #endif // I2C3_SDA Pin <0=>PH8 <1=>PC9 #define RTE_I2C3_SDA_PORT_ID 0 #if (RTE_I2C3_SDA_PORT_ID == 0) #define RTE_I2C3_SDA_PORT GPIOH #define RTE_I2C3_SDA_BIT 8 #elif (RTE_I2C3_SDA_PORT_ID == 1) #define RTE_I2C3_SDA_PORT GPIOC #define RTE_I2C3_SDA_BIT 9 #else #error "Invalid I2C3_SCL Pin Configuration!" #endif // DMA Rx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <2=>2 // Selects DMA Stream (only Stream 2 can be used) // Channel <3=>3 // Selects DMA Channel (only Channel 3 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_I2C3_RX_DMA 1 #define RTE_I2C3_RX_DMA_NUMBER 1 #define RTE_I2C3_RX_DMA_STREAM 2 #define RTE_I2C3_RX_DMA_CHANNEL 3 #define RTE_I2C3_RX_DMA_PRIORITY 0 // DMA Tx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <4=>4 // Selects DMA Stream (only Stream 4 can be used) // Channel <3=>3 // Selects DMA Channel (only Channel 3 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_I2C3_TX_DMA 1 #define RTE_I2C3_TX_DMA_NUMBER 1 #define RTE_I2C3_TX_DMA_STREAM 4 #define RTE_I2C3_TX_DMA_CHANNEL 3 #define RTE_I2C3_TX_DMA_PRIORITY 0 // // SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] // Configuration settings for Driver_SPI1 in component ::Drivers:SPI #define RTE_SPI1 0 // SPI1_NSS Pin // Configure Pin if exists // GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD // <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI // Selects Port Name // Bit <0-15> // Selects Port Bit // #define RTE_SPI1_NSS_PIN 1 #define RTE_SPI1_NSS_PORT GPIO_PORT(0) #define RTE_SPI1_NSS_BIT 4 // SPI1_SCK Pin <0=>PA5 <1=>PB3 #define RTE_SPI1_SCL_PORT_ID 0 #if (RTE_SPI1_SCL_PORT_ID == 0) #define RTE_SPI1_SCL_PORT GPIOA #define RTE_SPI1_SCL_BIT 5 #elif (RTE_SPI1_SCL_PORT_ID == 1) #define RTE_SPI1_SCL_PORT GPIOB #define RTE_SPI1_SCL_BIT 3 #else #error "Invalid SPI1_SCK Pin Configuration!" #endif // SPI1_MISO Pin <0=>PA6 <1=>PB4 #define RTE_SPI1_MISO_PORT_ID 0 #if (RTE_SPI1_MISO_PORT_ID == 0) #define RTE_SPI1_MISO_PORT GPIOA #define RTE_SPI1_MISO_BIT 6 #elif (RTE_SPI1_MISO_PORT_ID == 1) #define RTE_SPI1_MISO_PORT GPIOB #define RTE_SPI1_MISO_BIT 4 #else #error "Invalid SPI1_MISO Pin Configuration!" #endif // SPI1_MOSI Pin <0=>PA7 <1=>PB5 #define RTE_SPI1_MOSI_PORT_ID 0 #if (RTE_SPI1_MOSI_PORT_ID == 0) #define RTE_SPI1_MOSI_PORT GPIOA #define RTE_SPI1_MOSI_BIT 7 #elif (RTE_SPI1_MOSI_PORT_ID == 1) #define RTE_SPI1_MOSI_PORT GPIOB #define RTE_SPI1_MOSI_BIT 5 #else #error "Invalid SPI1_MISO Pin Configuration!" #endif // DMA Rx // Number <2=>2 // Selects DMA Number (only DMA2 can be used) // Stream <0=>0 <2=>2 // Selects DMA Stream (only Stream 0 or 2 can be used) // Channel <3=>3 // Selects DMA Channel (only Channel 3 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_SPI1_RX_DMA 1 #define RTE_SPI1_RX_DMA_NUMBER 2 #define RTE_SPI1_RX_DMA_STREAM 0 #define RTE_SPI1_RX_DMA_CHANNEL 3 #define RTE_SPI1_RX_DMA_PRIORITY 0 // DMA Tx // Number <2=>2 // Selects DMA Number (only DMA2 can be used) // Stream <3=>3 <5=>5 // Selects DMA Stream (only Stream 3 or 5 can be used) // Channel <3=>3 // Selects DMA Channel (only Channel 3 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_SPI1_TX_DMA 1 #define RTE_SPI1_TX_DMA_NUMBER 2 #define RTE_SPI1_TX_DMA_STREAM 5 #define RTE_SPI1_TX_DMA_CHANNEL 3 #define RTE_SPI1_TX_DMA_PRIORITY 0 // // SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] // Configuration settings for Driver_SPI2 in component ::Drivers:SPI #define RTE_SPI2 0 // SPI2_NSS Pin // Configure Pin if exists // GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD // <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI // Selects Port Name // Bit <0-15> // Selects Port Bit // #define RTE_SPI2_NSS_PIN 1 #define RTE_SPI2_NSS_PORT GPIO_PORT(1) #define RTE_SPI2_NSS_BIT 12 // SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PI1 #define RTE_SPI2_SCL_PORT_ID 0 #if (RTE_SPI2_SCL_PORT_ID == 0) #define RTE_SPI2_SCL_PORT GPIOB #define RTE_SPI2_SCL_BIT 10 #elif (RTE_SPI2_SCL_PORT_ID == 1) #define RTE_SPI2_SCL_PORT GPIOB #define RTE_SPI2_SCL_BIT 13 #elif (RTE_SPI2_SCL_PORT_ID == 2) #define RTE_SPI2_SCL_PORT GPIOI #define RTE_SPI2_SCL_BIT 1 #else #error "Invalid SPI2_SCK Pin Configuration!" #endif // SPI2_MISO Pin <0=>PB14 <1=>PC2 <2=>PI2 #define RTE_SPI2_MISO_PORT_ID 0 #if (RTE_SPI2_MISO_PORT_ID == 0) #define RTE_SPI2_MISO_PORT GPIOB #define RTE_SPI2_MISO_BIT 14 #elif (RTE_SPI2_MISO_PORT_ID == 1) #define RTE_SPI2_MISO_PORT GPIOC #define RTE_SPI2_MISO_BIT 2 #elif (RTE_SPI2_MISO_PORT_ID == 2) #define RTE_SPI2_MISO_PORT GPIOI #define RTE_SPI2_MISO_BIT 2 #else #error "Invalid SPI2_MISO Pin Configuration!" #endif // SPI2_MOSI Pin <0=>PB15 <1=>PC3 <2=>OI3 #define RTE_SPI2_MOSI_PORT_ID 0 #if (RTE_SPI2_MOSI_PORT_ID == 0) #define RTE_SPI2_MOSI_PORT GPIOB #define RTE_SPI2_MOSI_BIT 15 #elif (RTE_SPI2_MOSI_PORT_ID == 1) #define RTE_SPI2_MOSI_PORT GPIOC #define RTE_SPI2_MOSI_BIT 3 #elif (RTE_SPI2_MOSI_PORT_ID == 2) #define RTE_SPI2_MOSI_PORT GPIOI #define RTE_SPI2_MOSI_BIT 3 #else #error "Invalid SPI2_MISO Pin Configuration!" #endif // DMA Rx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <3=>3 // Selects DMA Stream (only Stream 3 can be used) // Channel <0=>0 // Selects DMA Channel (only Channel 0 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_SPI2_RX_DMA 1 #define RTE_SPI2_RX_DMA_NUMBER 1 #define RTE_SPI2_RX_DMA_STREAM 3 #define RTE_SPI2_RX_DMA_CHANNEL 0 #define RTE_SPI2_RX_DMA_PRIORITY 0 // DMA Tx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <4=>4 // Selects DMA Stream (only Stream 4 can be used) // Channel <0=>0 // Selects DMA Channel (only Channel 0 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_SPI2_TX_DMA 1 #define RTE_SPI2_TX_DMA_NUMBER 1 #define RTE_SPI2_TX_DMA_STREAM 4 #define RTE_SPI2_TX_DMA_CHANNEL 0 #define RTE_SPI2_TX_DMA_PRIORITY 0 // // SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] // Configuration settings for Driver_SPI3 in component ::Drivers:SPI #define RTE_SPI3 0 // SPI3_NSS Pin // Configure Pin if exists // GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD // <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI // Selects Port Name // Bit <0-15> // Selects Port Bit // #define RTE_SPI3_NSS_PIN 1 #define RTE_SPI3_NSS_PORT GPIO_PORT(0) #define RTE_SPI3_NSS_BIT 15 // SPI3_SCK Pin <0=>PB3 <1=>PC10 #define RTE_SPI3_SCL_PORT_ID 0 #if (RTE_SPI3_SCL_PORT_ID == 0) #define RTE_SPI3_SCL_PORT GPIOB #define RTE_SPI3_SCL_BIT 3 #elif (RTE_SPI3_SCL_PORT_ID == 1) #define RTE_SPI3_SCL_PORT GPIOC #define RTE_SPI3_SCL_BIT 10 #else #error "Invalid SPI3_SCK Pin Configuration!" #endif // SPI3_MISO Pin <0=>PB4 <1=>PC11 #define RTE_SPI3_MISO_PORT_ID 0 #if (RTE_SPI3_MISO_PORT_ID == 0) #define RTE_SPI3_MISO_PORT GPIOB #define RTE_SPI3_MISO_BIT 4 #elif (RTE_SPI3_MISO_PORT_ID == 1) #define RTE_SPI3_MISO_PORT GPIOC #define RTE_SPI3_MISO_BIT 11 #else #error "Invalid SPI3_MISO Pin Configuration!" #endif // SPI3_MOSI Pin <0=>PB5 <1=>PC12 #define RTE_SPI3_MOSI_PORT_ID 0 #if (RTE_SPI3_MOSI_PORT_ID == 0) #define RTE_SPI3_MOSI_PORT GPIOB #define RTE_SPI3_MOSI_BIT 5 #elif (RTE_SPI3_MOSI_PORT_ID == 1) #define RTE_SPI3_MOSI_PORT GPIOC #define RTE_SPI3_MOSI_BIT 12 #else #error "Invalid SPI3_MISO Pin Configuration!" #endif // DMA Rx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <0=>0 <2=>2 // Selects DMA Stream (only Stream 0 or 2 can be used) // Channel <0=>0 // Selects DMA Channel (only Channel 0 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_SPI3_RX_DMA 1 #define RTE_SPI3_RX_DMA_NUMBER 1 #define RTE_SPI3_RX_DMA_STREAM 0 #define RTE_SPI3_RX_DMA_CHANNEL 0 #define RTE_SPI3_RX_DMA_PRIORITY 0 // DMA Tx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <5=>5 <7=>7 // Selects DMA Stream (only Stream 5 or 7 can be used) // Channel <0=>0 // Selects DMA Channel (only Channel 0 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_SPI3_TX_DMA 1 #define RTE_SPI3_TX_DMA_NUMBER 1 #define RTE_SPI3_TX_DMA_STREAM 5 #define RTE_SPI3_TX_DMA_CHANNEL 0 #define RTE_SPI3_TX_DMA_PRIORITY 0 // // SPI4 (Serial Peripheral Interface 4) [Driver_SPI4] // Configuration settings for Driver_SPI4 in component ::Drivers:SPI #define RTE_SPI4 0 // SPI4_NSS Pin // Configure Pin if exists // GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD // <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI // Selects Port Name // Bit <0-15> // Selects Port Bit // #define RTE_SPI4_NSS_PIN 1 #define RTE_SPI4_NSS_PORT GPIO_PORT(4) #define RTE_SPI4_NSS_BIT 4 // SPI4_SCK Pin <0=>PE2 <1=>PE12 #define RTE_SPI4_SCL_PORT_ID 0 #if (RTE_SPI4_SCL_PORT_ID == 0) #define RTE_SPI4_SCL_PORT GPIOE #define RTE_SPI4_SCL_BIT 2 #elif (RTE_SPI4_SCL_PORT_ID == 1) #define RTE_SPI4_SCL_PORT GPIOE #define RTE_SPI4_SCL_BIT 12 #else #error "Invalid SPI4_SCK Pin Configuration!" #endif // SPI4_MISO Pin <0=>PE5 <1=>PE13 #define RTE_SPI4_MISO_PORT_ID 0 #if (RTE_SPI4_MISO_PORT_ID == 0) #define RTE_SPI4_MISO_PORT GPIOE #define RTE_SPI4_MISO_BIT 5 #elif (RTE_SPI4_MISO_PORT_ID == 1) #define RTE_SPI4_MISO_PORT GPIOE #define RTE_SPI4_MISO_BIT 13 #else #error "Invalid SPI4_MISO Pin Configuration!" #endif // SPI4_MOSI Pin <0=>PE6 <1=>PE14 #define RTE_SPI4_MOSI_PORT_ID 0 #if (RTE_SPI4_MOSI_PORT_ID == 0) #define RTE_SPI4_MOSI_PORT GPIOE #define RTE_SPI4_MOSI_BIT 6 #elif (RTE_SPI4_MOSI_PORT_ID == 1) #define RTE_SPI4_MOSI_PORT GPIOE #define RTE_SPI4_MOSI_BIT 14 #else #error "Invalid SPI4_MISO Pin Configuration!" #endif // DMA Rx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <0=>0 <2=>2 // Selects DMA Stream (only Stream 0 or 2 can be used) // Channel <0=>0 // Selects DMA Channel (only Channel 0 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_SPI4_RX_DMA 1 #define RTE_SPI4_RX_DMA_NUMBER 1 #define RTE_SPI4_RX_DMA_STREAM 0 #define RTE_SPI4_RX_DMA_CHANNEL 0 #define RTE_SPI4_RX_DMA_PRIORITY 0 // DMA Tx // Number <1=>1 // Selects DMA Number (only DMA1 can be used) // Stream <5=>5 <7=>7 // Selects DMA Stream (only Stream 5 or 7 can be used) // Channel <0=>0 // Selects DMA Channel (only Channel 0 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_SPI4_TX_DMA 1 #define RTE_SPI4_TX_DMA_NUMBER 1 #define RTE_SPI4_TX_DMA_STREAM 5 #define RTE_SPI4_TX_DMA_CHANNEL 0 #define RTE_SPI4_TX_DMA_PRIORITY 0 // // SPI5 (Serial Peripheral Interface 5) [Driver_SPI5] // Configuration settings for Driver_SPI5 in component ::Drivers:SPI #define RTE_SPI5 0 // SPI5_NSS Pin // Configure Pin if exists // GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD // <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI // Selects Port Name // Bit <0-15> // Selects Port Bit // #define RTE_SPI5_NSS_PIN 1 #define RTE_SPI5_NSS_PORT GPIO_PORT(5) #define RTE_SPI5_NSS_BIT 6 // SPI5_SCK Pin <0=>PF7 <1=>PH6 #define RTE_SPI5_SCL_PORT_ID 0 #if (RTE_SPI5_SCL_PORT_ID == 0) #define RTE_SPI5_SCL_PORT GPIOF #define RTE_SPI5_SCL_BIT 7 #elif (RTE_SPI5_SCL_PORT_ID == 1) #define RTE_SPI5_SCL_PORT GPIOH #define RTE_SPI5_SCL_BIT 6 #else #error "Invalid SPI5_SCK Pin Configuration!" #endif // SPI5_MISO Pin <0=>PF8 <1=>PH7 #define RTE_SPI5_MISO_PORT_ID 0 #if (RTE_SPI5_MISO_PORT_ID == 0) #define RTE_SPI5_MISO_PORT GPIOF #define RTE_SPI5_MISO_BIT 8 #elif (RTE_SPI5_MISO_PORT_ID == 1) #define RTE_SPI5_MISO_PORT GPIOH #define RTE_SPI5_MISO_BIT 7 #else #error "Invalid SPI5_MISO Pin Configuration!" #endif // SPI5_MOSI Pin <0=>PF9 <1=>PF11 #define RTE_SPI5_MOSI_PORT_ID 0 #if (RTE_SPI5_MOSI_PORT_ID == 0) #define RTE_SPI5_MOSI_PORT GPIOF #define RTE_SPI5_MOSI_BIT 9 #elif (RTE_SPI5_MOSI_PORT_ID == 1) #define RTE_SPI5_MOSI_PORT GPIOF #define RTE_SPI5_MOSI_BIT 11 #else #error "Invalid SPI5_MISO Pin Configuration!" #endif // DMA Rx // Number <2=>2 // Selects DMA Number (only DMA2 can be used) // Stream <3=>3 <5=>5 // Selects DMA Stream (only Stream 3 or 5 can be used) // Channel <2=>2 <7=>7 // Selects DMA Channel (only Channel 2 or 7 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_SPI5_RX_DMA 0 #define RTE_SPI5_RX_DMA_NUMBER 2 #define RTE_SPI5_RX_DMA_STREAM 3 #define RTE_SPI5_RX_DMA_CHANNEL 2 #define RTE_SPI5_RX_DMA_PRIORITY 0 // DMA Tx // Number <2=>2 // Selects DMA Number (only DMA2 can be used) // Stream <4=>4 <6=>6 // Selects DMA Stream (only Stream 4 or 6 can be used) // Channel <2=>2 <7=>7 // Selects DMA Channel (only Channel 2 or 7 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_SPI5_TX_DMA 0 #define RTE_SPI5_TX_DMA_NUMBER 2 #define RTE_SPI5_TX_DMA_STREAM 4 #define RTE_SPI5_TX_DMA_CHANNEL 2 #define RTE_SPI5_TX_DMA_PRIORITY 0 // // SPI6 (Serial Peripheral Interface 6) [Driver_SPI6] // Configuration settings for Driver_SPI6 in component ::Drivers:SPI #define RTE_SPI6 0 // SPI6_NSS Pin // Configure Pin if exists // GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD // <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI // Selects Port Name // Bit <0-15> // Selects Port Bit // #define RTE_SPI6_NSS_PIN 1 #define RTE_SPI6_NSS_PORT GPIO_PORT(6) #define RTE_SPI6_NSS_BIT 8 // SPI6_SCK Pin <0=>PG13 #define RTE_SPI6_SCL_PORT_ID 0 #if (RTE_SPI6_SCL_PORT_ID == 0) #define RTE_SPI6_SCL_PORT GPIOG #define RTE_SPI6_SCL_BIT 13 #else #error "Invalid SPI6_SCK Pin Configuration!" #endif // SPI6_MISO Pin <0=>PG12 #define RTE_SPI6_MISO_PORT_ID 0 #if (RTE_SPI6_MISO_PORT_ID == 0) #define RTE_SPI6_MISO_PORT GPIOG #define RTE_SPI6_MISO_BIT 12 #else #error "Invalid SPI6_MISO Pin Configuration!" #endif // SPI6_MOSI Pin <0=>PG14 #define RTE_SPI6_MOSI_PORT_ID 0 #if (RTE_SPI6_MOSI_PORT_ID == 0) #define RTE_SPI6_MOSI_PORT GPIOG #define RTE_SPI6_MOSI_BIT 14 #else #error "Invalid SPI6_MISO Pin Configuration!" #endif // DMA Rx // Number <2=>2 // Selects DMA Number (only DMA2 can be used) // Stream <6=>6 // Selects DMA Stream (only Stream 6 can be used) // Channel <1=>1 // Selects DMA Channel (only Channel 1 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_SPI6_RX_DMA 0 #define RTE_SPI6_RX_DMA_NUMBER 2 #define RTE_SPI6_RX_DMA_STREAM 6 #define RTE_SPI6_RX_DMA_CHANNEL 1 #define RTE_SPI6_RX_DMA_PRIORITY 0 // DMA Tx // Number <2=>2 // Selects DMA Number (only DMA2 can be used) // Stream <5=>5 // Selects DMA Stream (only Stream 5 can be used) // Channel <1=>1 // Selects DMA Channel (only Channel 1 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_SPI6_TX_DMA 0 #define RTE_SPI6_TX_DMA_NUMBER 2 #define RTE_SPI6_TX_DMA_STREAM 5 #define RTE_SPI6_TX_DMA_CHANNEL 1 #define RTE_SPI6_TX_DMA_PRIORITY 0 // // SDIO (Secure Digital Input/Output) [Driver_MCI0] // Configuration settings for Driver_MCI0 in component ::Drivers:MCI #define RTE_SDIO 0 // SDIO_CD (Card Detect) Pin // Configure Pin if exists // GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) // Active State <0=>Low <1=>High // Selects Active State Logical Level // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD // <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI // Selects Port Name // Bit <0-15> // Selects Port Bit // #define RTE_SDIO_CD_PIN 1 #define RTE_SDIO_CD_ACTIVE 0 #define RTE_SDIO_CD_PORT GPIO_PORT(7) #define RTE_SDIO_CD_BIT 15 // SDIO_WP (Write Protect) Pin // Configure Pin if exists // GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) // Active State <0=>Low <1=>High // Selects Active State Logical Level // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD // <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI // Selects Port Name // Bit <0-15> // Selects Port Bit // #define RTE_SDIO_WP_PIN 0 #define RTE_SDIO_WP_ACTIVE 0 #define RTE_SDIO_WP_PORT GPIO_PORT(7) #define RTE_SDIO_WP_BIT 16 // SDIO Bus // SDIO_CK Pin <0=>PC12 #define RTE_SDIO_CK_PORT_ID 0 #if (RTE_SDIO_CK_PORT_ID == 0) #define RTE_SDIO_CK_PORT GPIOC #define RTE_SDIO_CK_PIN 12 #else #error "Invalid SDIO_CK Pin Configuration!" #endif // SDIO_CMD Pin <0=>PD2 #define RTE_SDIO_CMD_PORT_ID 0 #if (RTE_SDIO_CMD_PORT_ID == 0) #define RTE_SDIO_CMD_PORT GPIOD #define RTE_SDIO_CMD_PIN 2 #else #error "Invalid SDIO_CDM Pin Configuration!" #endif // SDIO_D0 Pin <0=>PC8 #define RTE_SDIO_D0_PORT_ID 0 #if (RTE_SDIO_D0_PORT_ID == 0) #define RTE_SDIO_D0_PORT GPIOC #define RTE_SDIO_D0_PIN 8 #else #error "Invalid SDIO_D0 Pin Configuration!" #endif // SDIO_D1 Pin <0=>PC9 #define RTE_SDIO_D1_PORT_ID 0 #if (RTE_SDIO_D1_PORT_ID == 0) #define RTE_SDIO_D1_PORT GPIOC #define RTE_SDIO_D1_PIN 9 #else #error "Invalid SDIO_D1 Pin Configuration!" #endif // SDIO_D2 Pin <0=>PC10 #define RTE_SDIO_D2_PORT_ID 0 #if (RTE_SDIO_D2_PORT_ID == 0) #define RTE_SDIO_D2_PORT GPIOC #define RTE_SDIO_D2_PIN 10 #else #error "Invalid SDIO_D2 Pin Configuration!" #endif // SDIO_D3 Pin <0=>PC11 #define RTE_SDIO_D3_PORT_ID 0 #if (RTE_SDIO_D3_PORT_ID == 0) #define RTE_SDIO_D3_PORT GPIOC #define RTE_SDIO_D3_PIN 11 #else #error "Invalid SDIO_D3 Pin Configuration!" #endif // SDIO_D4 Pin <0=>PB8 #define RTE_SDIO_D4_PORT_ID 0 #if (RTE_SDIO_D4_PORT_ID == 0) #define RTE_SDIO_D4_PORT GPIOB #define RTE_SDIO_D4_PIN 8 #else #error "Invalid SDIO_D4 Pin Configuration!" #endif // SDIO_D5 Pin <0=>PB9 #define RTE_SDIO_D5_PORT_ID 0 #if (RTE_SDIO_D5_PORT_ID == 0) #define RTE_SDIO_D5_PORT GPIOB #define RTE_SDIO_D5_PIN 9 #else #error "Invalid SDIO_D5 Pin Configuration!" #endif // SDIO_D6 Pin <0=>PC6 #define RTE_SDIO_D6_PORT_ID 0 #if (RTE_SDIO_D6_PORT_ID == 0) #define RTE_SDIO_D6_PORT GPIOC #define RTE_SDIO_D6_PIN 6 #else #error "Invalid SDIO_D6 Pin Configuration!" #endif // SDIO_D7 Pin <0=>PC7 #define RTE_SDIO_D7_PORT_ID 0 #if (RTE_SDIO_D7_PORT_ID == 0) #define RTE_SDIO_D7_PORT GPIOC #define RTE_SDIO_D7_PIN 7 #else #error "Invalid SDIO_D7 Pin Configuration!" #endif // // DMA // Number <2=>2 // Selects DMA Number (only DMA2 can be used) // Stream <3=>3 <6=>6 // Selects DMA Stream (only Stream 3 or 6 can be used) // Channel <4=>4 // Selects DMA Channel (only Channel 4 can be used) // Priority <0=>Low <1=>Medium <2=>High <3=>Very High // Selects DMA Priority // #define RTE_SDIO_DMA 1 #define RTE_SDIO_DMA_NUMBER 2 #define RTE_SDIO_DMA_STREAM 3 #define RTE_SDIO_DMA_CHANNEL 4 #define RTE_SDIO_DMA_PRIORITY 0 // // ETH (Ethernet Interface) [Driver_ETH_MAC0] // Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC #define RTE_ETH 0 // MII (Media Independent Interface) #define RTE_ETH_MII 1 // ETH_MII_TX_CLK Pin <0=>PC3 #define RTE_ETH_MII_TX_CLK_PORT_ID 0 #if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) #define RTE_ETH_MII_TX_CLK_PORT GPIOC #define RTE_ETH_MII_TX_CLK_PIN 3 #else #error "Invalid ETH_MII_TX_CLK Pin Configuration!" #endif // ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 #define RTE_ETH_MII_TXD0_PORT_ID 0 #if (RTE_ETH_MII_TXD0_PORT_ID == 0) #define RTE_ETH_MII_TXD0_PORT GPIOB #define RTE_ETH_MII_TXD0_PIN 12 #elif (RTE_ETH_MII_TXD0_PORT_ID == 1) #define RTE_ETH_MII_TXD0_PORT GPIOG #define RTE_ETH_MII_TXD0_PIN 13 #else #error "Invalid ETH_MII_TXD0 Pin Configuration!" #endif // ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 #define RTE_ETH_MII_TXD1_PORT_ID 0 #if (RTE_ETH_MII_TXD1_PORT_ID == 0) #define RTE_ETH_MII_TXD1_PORT GPIOB #define RTE_ETH_MII_TXD1_PIN 13 #elif (RTE_ETH_MII_TXD1_PORT_ID == 1) #define RTE_ETH_MII_TXD1_PORT GPIOG #define RTE_ETH_MII_TXD1_PIN 14 #else #error "Invalid ETH_MII_TXD1 Pin Configuration!" #endif // ETH_MII_TXD2 Pin <0=>PC2 #define RTE_ETH_MII_TXD2_PORT_ID 0 #if (RTE_ETH_MII_TXD2_PORT_ID == 0) #define RTE_ETH_MII_TXD2_PORT GPIOC #define RTE_ETH_MII_TXD2_PIN 2 #else #error "Invalid ETH_MII_TXD2 Pin Configuration!" #endif // ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 #define RTE_ETH_MII_TXD3_PORT_ID 0 #if (RTE_ETH_MII_TXD3_PORT_ID == 0) #define RTE_ETH_MII_TXD3_PORT GPIOB #define RTE_ETH_MII_TXD3_PIN 8 #elif (RTE_ETH_MII_TXD3_PORT_ID == 1) #define RTE_ETH_MII_TXD3_PORT GPIOE #define RTE_ETH_MII_TXD3_PIN 2 #else #error "Invalid ETH_MII_TXD3 Pin Configuration!" #endif // ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 #define RTE_ETH_MII_TX_EN_PORT_ID 0 #if (RTE_ETH_MII_TX_EN_PORT_ID == 0) #define RTE_ETH_MII_TX_EN_PORT GPIOB #define RTE_ETH_MII_TX_EN_PIN 11 #elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) #define RTE_ETH_MII_TX_EN_PORT GPIOG #define RTE_ETH_MII_TX_EN_PIN 11 #else #error "Invalid ETH_MII_TX_EN Pin Configuration!" #endif // ETH_MII_RX_CLK Pin <0=>PA1 #define RTE_ETH_MII_RX_CLK_PORT_ID 0 #if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) #define RTE_ETH_MII_RX_CLK_PORT GPIOA #define RTE_ETH_MII_RX_CLK_PIN 1 #else #error "Invalid ETH_MII_RX_CLK Pin Configuration!" #endif // ETH_MII_RXD0 Pin <0=>PC4 #define RTE_ETH_MII_RXD0_PORT_ID 0 #if (RTE_ETH_MII_RXD0_PORT_ID == 0) #define RTE_ETH_MII_RXD0_PORT GPIOC #define RTE_ETH_MII_RXD0_PIN 4 #else #error "Invalid ETH_MII_RXD0 Pin Configuration!" #endif // ETH_MII_RXD1 Pin <0=>PC5 #define RTE_ETH_MII_RXD1_PORT_ID 0 #if (RTE_ETH_MII_RXD1_PORT_ID == 0) #define RTE_ETH_MII_RXD1_PORT GPIOC #define RTE_ETH_MII_RXD1_PIN 5 #else #error "Invalid ETH_MII_RXD1 Pin Configuration!" #endif // ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 #define RTE_ETH_MII_RXD2_PORT_ID 0 #if (RTE_ETH_MII_RXD2_PORT_ID == 0) #define RTE_ETH_MII_RXD2_PORT GPIOB #define RTE_ETH_MII_RXD2_PIN 0 #elif (RTE_ETH_MII_RXD2_PORT_ID == 1) #define RTE_ETH_MII_RXD2_PORT GPIOH #define RTE_ETH_MII_RXD2_PIN 6 #else #error "Invalid ETH_MII_RXD2 Pin Configuration!" #endif // ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 #define RTE_ETH_MII_RXD3_PORT_ID 0 #if (RTE_ETH_MII_RXD3_PORT_ID == 0) #define RTE_ETH_MII_RXD3_PORT GPIOB #define RTE_ETH_MII_RXD3_PIN 1 #elif (RTE_ETH_MII_RXD3_PORT_ID == 1) #define RTE_ETH_MII_RXD3_PORT GPIOH #define RTE_ETH_MII_RXD3_PIN 7 #else #error "Invalid ETH_MII_RXD3 Pin Configuration!" #endif // ETH_MII_RX_DV Pin <0=>PA7 #define RTE_ETH_MII_RX_DV_PORT_ID 0 #if (RTE_ETH_MII_RX_DV_PORT_ID == 0) #define RTE_ETH_MII_RX_DV_PORT GPIOA #define RTE_ETH_MII_RX_DV_PIN 7 #else #error "Invalid ETH_MII_RX_DV Pin Configuration!" #endif // ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10 #define RTE_ETH_MII_RX_ER_PORT_ID 0 #if (RTE_ETH_MII_RX_ER_PORT_ID == 0) #define RTE_ETH_MII_RX_ER_PORT GPIOB #define RTE_ETH_MII_RX_ER_PIN 10 #elif (RTE_ETH_MII_RXD3_PORT_ID == 1) #define RTE_ETH_MII_RX_ER_PORT GPIOI #define RTE_ETH_MII_RX_ER_PIN 10 #else #error "Invalid ETH_MII_RX_ER Pin Configuration!" #endif // ETH_MII_CRS Pin <0=>PA0 <1=>PH2 #define RTE_ETH_MII_CRS_PORT_ID 0 #if (RTE_ETH_MII_CRS_PORT_ID == 0) #define RTE_ETH_MII_CRS_PORT GPIOA #define RTE_ETH_MII_CRS_PIN 0 #elif (RTE_ETH_MII_CRS_PORT_ID == 1) #define RTE_ETH_MII_CRS_PORT GPIOH #define RTE_ETH_MII_CRS_PIN 2 #else #error "Invalid ETH_MII_CRS Pin Configuration!" #endif // ETH_MII_COL Pin <0=>PA3 <1=>PH3 #define RTE_ETH_MII_COL_PORT_ID 0 #if (RTE_ETH_MII_COL_PORT_ID == 0) #define RTE_ETH_MII_COL_PORT GPIOA #define RTE_ETH_MII_COL_PIN 3 #elif (RTE_ETH_MII_COL_PORT_ID == 1) #define RTE_ETH_MII_COL_PORT GPIOH #define RTE_ETH_MII_COL_PIN 3 #else #error "Invalid ETH_MII_COL Pin Configuration!" #endif // // RMII (Reduced Media Independent Interface) #define RTE_ETH_RMII 0 // ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 #define RTE_ETH_RMII_TXD0_PORT_ID 0 #if (RTE_ETH_RMII_TXD0_PORT_ID == 0) #define RTE_ETH_RMII_TXD0_PORT GPIOB #define RTE_ETH_RMII_TXD0_PIN 12 #elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) #define RTE_ETH_RMII_TXD0_PORT GPIOG #define RTE_ETH_RMII_TXD0_PIN 13 #else #error "Invalid ETH_RMII_TXD0 Pin Configuration!" #endif // ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 #define RTE_ETH_RMII_TXD1_PORT_ID 0 #if (RTE_ETH_RMII_TXD1_PORT_ID == 0) #define RTE_ETH_RMII_TXD1_PORT GPIOB #define RTE_ETH_RMII_TXD1_PIN 13 #elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) #define RTE_ETH_RMII_TXD1_PORT GPIOG #define RTE_ETH_RMII_TXD1_PIN 14 #else #error "Invalid ETH_RMII_TXD1 Pin Configuration!" #endif // ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 #define RTE_ETH_RMII_TX_EN_PORT_ID 0 #if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) #define RTE_ETH_RMII_TX_EN_PORT GPIOB #define RTE_ETH_RMII_TX_EN_PIN 11 #elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) #define RTE_ETH_RMII_TX_EN_PORT GPIOG #define RTE_ETH_RMII_TX_EN_PIN 11 #else #error "Invalid ETH_RMII_TX_EN Pin Configuration!" #endif // ETH_RMII_RXD0 Pin <0=>PC4 #define RTE_ETH_RMII_RXD0_PORT_ID 0 #if (RTE_ETH_RMII_RXD0_PORT_ID == 0) #define RTE_ETH_RMII_RXD0_PORT GPIOC #define RTE_ETH_RMII_RXD0_PIN 4 #else #error "Invalid ETH_RMII_RXD0 Pin Configuration!" #endif // ETH_RMII_RXD1 Pin <0=>PC5 #define RTE_ETH_RMII_RXD1_PORT_ID 0 #if (RTE_ETH_RMII_RXD1_PORT_ID == 0) #define RTE_ETH_RMII_RXD1_PORT GPIOC #define RTE_ETH_RMII_RXD1_PIN 5 #else #error "Invalid ETH_RMII_RXD1 Pin Configuration!" #endif // ETH_RMII_REF_CLK Pin <0=>PA1 #define RTE_ETH_RMII_REF_CLK_PORT_ID 0 #if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) #define RTE_ETH_RMII_REF_CLK_PORT GPIOA #define RTE_ETH_RMII_REF_CLK_PIN 1 #else #error "Invalid ETH_RMII_REF_CLK Pin Configuration!" #endif // ETH_RMII_CRS_DV Pin <0=>PA7 #define RTE_ETH_RMII_CRS_DV_PORT_ID 0 #if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) #define RTE_ETH_RMII_CRS_DV_PORT GPIOA #define RTE_ETH_RMII_CRS_DV_PIN 7 #else #error "Invalid ETH_RMII_CRS_DV Pin Configuration!" #endif // // Management Data Interface // ETH_MDC Pin <0=>PC1 #define RTE_ETH_MDI_MDC_PORT_ID 0 #if (RTE_ETH_MDI_MDC_PORT_ID == 0) #define RTE_ETH_MDI_MDC_PORT GPIOC #define RTE_ETH_MDI_MDC_PIN 1 #else #error "Invalid ETH_MDC Pin Configuration!" #endif // ETH_MDIO Pin <0=>PA2 #define RTE_ETH_MDI_MDIO_PORT_ID 0 #if (RTE_ETH_MDI_MDIO_PORT_ID == 0) #define RTE_ETH_MDI_MDIO_PORT GPIOA #define RTE_ETH_MDI_MDIO_PIN 2 #else #error "Invalid ETH_MDIO Pin Configuration!" #endif // // Reference 25MHz/50MHz Clock generation #define RTE_ETH_REF_CLOCK 1 // MCO Pin <0=>PA2 <1=>PC9 #define RTE_ETH_REF_CLOCK_PORT_ID 0 #if (RTE_ETH_REF_CLOCK_PORT_ID == 0) #define RTE_ETH_REF_CLOCK_PORT GPIOA #define RTE_ETH_REF_CLOCK_PIN 8 #elif (RTE_ETH_REF_CLOCK_PORT_ID == 1) #define RTE_ETH_REF_CLOCK_PORT GPIOC #define RTE_ETH_REF_CLOCK_PIN 9 #else #error "Invalid MCO Pin Configuration!" #endif // // // USB OTG Full-speed #define RTE_USB_OTG_FS 0 // Device [Driver_USBD0] // Configuration settings for Driver_USBD0 in component ::Drivers:USB Device #define RTE_USB_OTG_FS_DEV 1 // Endpoints // Reduce memory requirements of Driver by disabling unused endpoints // Endpoint 1 // Bulk OUT // Bulk IN // Interrupt OUT // Interrupt IN // Isochronous OUT // Isochronous IN // // Endpoint 2 // Bulk OUT // Bulk IN // Interrupt OUT // Interrupt IN // Isochronous OUT // Isochronous IN // // Endpoint 3 // Bulk OUT // Bulk IN // Interrupt OUT // Interrupt IN // Isochronous OUT // Isochronous IN // // #define RTE_USB_OTG_FS_DEV_EP 0x0000000F #define RTE_USB_OTG_FS_DEV_EP_BULK 0x000E000E #define RTE_USB_OTG_FS_DEV_EP_INT 0x000E000E #define RTE_USB_OTG_FS_DEV_EP_ISO 0x000E000E // // Host [Driver_USBH0] // Configuration settings for Driver_USBH0 in component ::Drivers:USB Host #define RTE_USB_OTG_FS_HOST 1 // VBUS Power On/Off Pin // Configure Pin for driving VBUS // GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) // Active State <0=>Low <1=>High // Selects Active State Logical Level // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD // <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI // Selects Port Name // Bit <0-15> // Selects Port Bit // #define RTE_OTG_FS_VBUS_PIN 1 #define RTE_OTG_FS_VBUS_ACTIVE 0 #define RTE_OTG_FS_VBUS_PORT GPIO_PORT(7) #define RTE_OTG_FS_VBUS_BIT 5 // Overcurrent Detection Pin // Configure Pin for overcurrent detection // GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) // Active State <0=>Low <1=>High // Selects Active State Logical Level // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD // <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI // Selects Port Name // Bit <0-15> // Selects Port Bit // #define RTE_OTG_FS_OC_PIN 1 #define RTE_OTG_FS_OC_ACTIVE 0 #define RTE_OTG_FS_OC_PORT GPIO_PORT(5) #define RTE_OTG_FS_OC_BIT 11 // // // USB OTG High-speed #define RTE_USB_OTG_HS 0 // PHY (Physical Layer) // PHY Interface // <0=>On-chip full-speed PHY // <1=>External ULPI high-speed PHY #define RTE_USB_OTG_HS_PHY 1 // External ULPI Pins (UTMI+ Low Pin Interface) // OTG_HS_ULPI_CK Pin <0=>PA5 #define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 #if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) #define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA #define RTE_USB_OTG_HS_ULPI_CK_PIN 5 #else #error "Invalid OTG_HS_ULPI_CK Pin Configuration!" #endif // OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 #define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 #if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) #define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI #define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 #elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) #define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC #define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 #else #error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" #endif // OTG_HS_ULPI_STP Pin <0=>PC0 #define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 #if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) #define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC #define RTE_USB_OTG_HS_ULPI_STP_PIN 0 #else #error "Invalid OTG_HS_ULPI_STP Pin Configuration!" #endif // OTG_HS_ULPI_NXT Pin <0=>PC2 <1=>PH4 #define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 #if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) #define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC #define RTE_USB_OTG_HS_ULPI_NXT_PIN 2 #elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) #define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH #define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 #else #error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" #endif // OTG_HS_ULPI_D0 Pin <0=>PA3 #define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 #if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) #define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA #define RTE_USB_OTG_HS_ULPI_D0_PIN 3 #else #error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" #endif // OTG_HS_ULPI_D1 Pin <0=>PB0 #define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 #if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) #define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB #define RTE_USB_OTG_HS_ULPI_D1_PIN 0 #else #error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" #endif // OTG_HS_ULPI_D2 Pin <0=>PB1 #define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 #if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) #define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB #define RTE_USB_OTG_HS_ULPI_D2_PIN 1 #else #error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" #endif // OTG_HS_ULPI_D3 Pin <0=>PB10 #define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 #if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) #define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB #define RTE_USB_OTG_HS_ULPI_D3_PIN 10 #else #error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" #endif // OTG_HS_ULPI_D4 Pin <0=>PB11 #define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 #if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) #define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB #define RTE_USB_OTG_HS_ULPI_D4_PIN 11 #else #error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" #endif // OTG_HS_ULPI_D5 Pin <0=>PB12 #define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 #if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) #define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB #define RTE_USB_OTG_HS_ULPI_D5_PIN 12 #else #error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" #endif // OTG_HS_ULPI_D6 Pin <0=>PB13 #define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 #if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) #define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB #define RTE_USB_OTG_HS_ULPI_D6_PIN 13 #else #error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" #endif // OTG_HS_ULPI_D7 Pin <0=>PB5 #define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 #if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) #define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB #define RTE_USB_OTG_HS_ULPI_D7_PIN 5 #else #error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" #endif // // // Device [Driver_USBD1] // Configuration settings for Driver_USBD1 in component ::Drivers:USB Device #define RTE_USB_OTG_HS_DEV 1 // Endpoints // Reduce memory requirements of Driver by disabling unused endpoints // Endpoint 1 // Bulk OUT // Bulk IN // Interrupt OUT // Interrupt IN // Isochronous OUT // Isochronous IN // // Endpoint 2 // Bulk OUT // Bulk IN // Interrupt OUT // Interrupt IN // Isochronous OUT // Isochronous IN // // Endpoint 3 // Bulk OUT // Bulk IN // Interrupt OUT // Interrupt IN // Isochronous OUT // Isochronous IN // // Endpoint 4 // Bulk OUT // Bulk IN // Interrupt OUT // Interrupt IN // Isochronous OUT // Isochronous IN // // Endpoint 5 // Bulk OUT // Bulk IN // Interrupt OUT // Interrupt IN // Isochronous OUT // Isochronous IN // // #define RTE_USB_OTG_HS_DEV_EP 0x0000003F #define RTE_USB_OTG_HS_DEV_EP_BULK 0x003E003E #define RTE_USB_OTG_HS_DEV_EP_INT 0x003E003E #define RTE_USB_OTG_HS_DEV_EP_ISO 0x003E003E // // Host [Driver_USBH1] // Configuration settings for Driver_USBH1 in component ::Drivers:USB Host #define RTE_USB_OTG_HS_HOST 1 // VBUS Power On/Off Pin // Configure Pin for driving VBUS // GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) // Active State <0=>Low <1=>High // Selects Active State Logical Level // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD // <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI // Selects Port Name // Bit <0-15> // Selects Port Bit // #define RTE_OTG_HS_VBUS_PIN 1 #define RTE_OTG_HS_VBUS_ACTIVE 0 #define RTE_OTG_HS_VBUS_PORT GPIO_PORT(2) #define RTE_OTG_HS_VBUS_BIT 2 // Overcurrent Detection Pin // Configure Pin for overcurrent detection // GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) // Active State <0=>Low <1=>High // Selects Active State Logical Level // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD // <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI // Selects Port Name // Bit <0-15> // Selects Port Bit // #define RTE_OTG_HS_OC_PIN 1 #define RTE_OTG_HS_OC_ACTIVE 0 #define RTE_OTG_HS_OC_PORT GPIO_PORT(5) #define RTE_OTG_HS_OC_BIT 12 // // // EXTI (External Interrupt/Event Controller) #define RTE_EXTI 0 // EXTI0 Line #define RTE_EXTI0 0 // Pin <0=>PA0 <1=>PB0 <2=>PC0 <3=>PD0 <4=>PE0 <5=>PF0 <6=>PG0 <7=>PH0 <8=>PI0 #define RTE_EXTI0_PIN 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI0_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI0_TRIGGER 0 // // EXTI1 Line #define RTE_EXTI1 0 // Pin <0=>PA1 <1=>PB1 <2=>PC1 <3=>PD1 <4=>PE1 <5=>PF1 <6=>PG1 <7=>PH1 <8=>PI1 #define RTE_EXTI1_PIN 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI1_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI1_TRIGGER 0 // // EXTI2 Line #define RTE_EXTI2 0 // Pin <0=>PA2 <1=>PB2 <2=>PC2 <3=>PD2 <4=>PE2 <5=>PF2 <6=>PG2 <7=>PH2 <8=>PI2 #define RTE_EXTI2_PIN 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI2_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI2_TRIGGER 0 // // EXTI3 Line #define RTE_EXTI3 0 // Pin <0=>PA3 <1=>PB3 <2=>PC3 <3=>PD3 <4=>PE3 <5=>PF3 <6=>PG3 <7=>PH3 <8=>PI3 #define RTE_EXTI3_PIN 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI3_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI3_TRIGGER 0 // // EXTI4 Line #define RTE_EXTI4 0 // Pin <0=>PA4 <1=>PB4 <2=>PC4 <3=>PD4 <4=>PE4 <5=>PF4 <6=>PG4 <7=>PH4 <8=>PI4 #define RTE_EXTI4_PIN 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI4_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI4_TRIGGER 0 // // EXTI5 Line #define RTE_EXTI5 0 // Pin <0=>PA5 <1=>PB5 <2=>PC5 <3=>PD5 <4=>PE5 <5=>PF5 <6=>PG5 <7=>PH5 <8=>PI5 #define RTE_EXTI5_PIN 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI5_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI5_TRIGGER 0 // // EXTI6 Line #define RTE_EXTI6 0 // Pin <0=>PA6 <1=>PB6 <2=>PC6 <3=>PD6 <4=>PE6 <5=>PF6 <6=>PG6 <7=>PH6 <8=>PI6 #define RTE_EXTI6_PIN 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI6_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI6_TRIGGER 0 // // EXTI7 Line #define RTE_EXTI7 0 // Pin <0=>PA7 <1=>PB7 <2=>PC7 <3=>PD7 <4=>PE7 <5=>PF7 <6=>PG7 <7=>PH7 <8=>PI7 #define RTE_EXTI7_PIN 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI7_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI7_TRIGGER 0 // // EXTI8 Line #define RTE_EXTI8 0 // Pin <0=>PA8 <1=>PB8 <2=>PC8 <3=>PD8 <4=>PE8 <5=>PF8 <6=>PG8 <7=>PH8 <8=>PI8 #define RTE_EXTI8_PIN 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI8_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI8_TRIGGER 0 // // EXTI9 Line #define RTE_EXTI9 0 // Pin <0=>PA9 <1=>PB9 <2=>PC9 <3=>PD9 <4=>PE9 <5=>PF9 <6=>PG9 <7=>PH9 <8=>PI9 #define RTE_EXTI9_PIN 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI9_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI9_TRIGGER 0 // // EXTI10 Line #define RTE_EXTI10 0 // Pin <0=>PA10 <1=>PB10 <2=>PC10 <3=>PD10 <4=>PE10 <5=>PF10 <6=>PG10 <7=>PH10 <8=>PI10 #define RTE_EXTI10_PIN 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI10_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI10_TRIGGER 0 // // EXTI11 Line #define RTE_EXTI11 0 // Pin <0=>PA11 <1=>PB11 <2=>PC11 <3=>PD11 <4=>PE11 <5=>PF11 <6=>PG11 <7=>PH11 <8=>PI11 #define RTE_EXTI11_PIN 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI11_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI11_TRIGGER 0 // // EXTI12 Line #define RTE_EXTI12 0 // Pin <0=>PA12 <1=>PB12 <2=>PC12 <3=>PD12 <4=>PE12 <5=>PF12 <6=>PG12 <7=>PH12 #define RTE_EXTI12_PIN 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI12_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI12_TRIGGER 0 // // EXTI13 Line #define RTE_EXTI13 0 // Pin <0=>PA13 <1=>PB13 <2=>PC13 <3=>PD13 <4=>PE13 <5=>PF13 <6=>PG13 <7=>PH13 #define RTE_EXTI13_PIN 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI13_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI13_TRIGGER 0 // // EXTI14 Line #define RTE_EXTI14 0 // Pin <0=>PA14 <1=>PB14 <2=>PC14 <3=>PD14 <4=>PE14 <5=>PF14 <6=>PG14 <7=>PH14 #define RTE_EXTI14_PIN 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI14_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI14_TRIGGER 0 // // EXTI15 Line #define RTE_EXTI15 0 // Pin <0=>PA15 <1=>PB15 <2=>PC15 <3=>PD15 <4=>PE15 <5=>PF15 <6=>PG15 <7=>PH15 #define RTE_EXTI15_PIN 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI15_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI15_TRIGGER 0 // // EXTI16 Line: PVD Output #define RTE_EXTI16 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI16_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI16_TRIGGER 0 // // EXTI17 Line: RTC Alarm #define RTE_EXTI17 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI17_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI17_TRIGGER 0 // // EXTI18 Line: USB OTG FS Wakeup #define RTE_EXTI18 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI18_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI18_TRIGGER 0 // // EXTI19 Line: Ethernet Wakeup #define RTE_EXTI19 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI19_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI19_TRIGGER 0 // // EXTI20 Line: USB OTG HS Wakeup #define RTE_EXTI20 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI20_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI20_TRIGGER 0 // // EXTI21 Line: RTC Tamper and TimeStamp #define RTE_EXTI21 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI21_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI21_TRIGGER 0 // // EXTI22 Line: RTC Wakeup #define RTE_EXTI22 0 // Mode <0=>Interrupt <1=>Event #define RTE_EXTI22_MODE 0 // Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge #define RTE_EXTI22_TRIGGER 0 // // // FSMC (Flexible Static Memory Controller) #define RTE_FSMC 0 // Pin Configuration // Configure Pins #define RTE_FSMC_PINS 0 // Address Bus Pins // <0=>A[17:16] // <1=>A[10:0] <2=>A[15:0] <3=>A[16:0] <4=>A[17:0] // <5=>A[18:0] <6=>A[19:0] <7=>A[20:0] <8=>A[21:0] // <9=>A[22:0] <10=>A[23:0] <11=>A[24:0] <12=>A[25:0] #define RTE_FSMC_ABUS_PINS 10 // Data Bus Pins <0=>D[7:0] <1=>D[15:0] #define RTE_FSMC_DBUS_PINS 0 // FSMC_NOE Pin #define RTE_FSMC_NOE_PIN 0 // FSMC_NWE Pin #define RTE_FSMC_NWE_PIN 0 // FSMC_NBL0 Pin #define RTE_FSMC_NBL0_PIN 0 // FSMC_NBL1 Pin #define RTE_FSMC_NBL1_PIN 0 // FSMC_NL Pin #define RTE_FSMC_NL_PIN 0 // FSMC_NWAIT Pin #define RTE_FSMC_NWAIT_PIN 0 // FSMC_CLK Pin #define RTE_FSMC_CLK_PIN 0 // FSMC_NE1/NCE2 Pin #define RTE_FSMC_NE1_PIN 0 // FSMC_NE2/NCE3 Pin #define RTE_FSMC_NE2_PIN 0 // FSMC_NE3/NCE4_1 Pin #define RTE_FSMC_NE3_PIN 0 // FSMC_NE4 Pin #define RTE_FSMC_NE4_PIN 0 // FSMC_NCE4_2 Pin #define RTE_FSMC_NCE42_PIN 0 // FSMC_INT2 Pin #define RTE_FSMC_INT2_PIN 0 // FSMC_INT3 Pin #define RTE_FSMC_INT3_PIN 0 // FSMC_INTR Pin #define RTE_FSMC_INTR_PIN 0 // FSMC_NIORD Pin #define RTE_FSMC_NIORD_PIN 0 // FSMC_NIOWR Pin #define RTE_FSMC_NIOWR_PIN 0 // FSMC_NREG Pin #define RTE_FSMC_NREG_PIN 0 // FSMC_CD Pin #define RTE_FSMC_CD_PIN 0 // // NOR Flash / PSRAM Controller // FSMC_NE1 Chip Select // Configure Device on Chip Select FSMC_NE1 #define RTE_FSMC_NE1 0 // Chip-select control // CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write // For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash // memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. // ASYNCWAIT: Wait signal during asynchronous transfer // Enables the FSMC to use the wait signal even during an asynchronous protocol. // EXTMOD: Extended mode enable // Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. // WAITEN: Wait enable // For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. // WREN: Write enable // Enable/disable write operations in the current bank by the FSMC // WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state // For memory access in burst mode, the NWAIT signal indicates whether the data from the memory // are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted // by the memory one clock cycle before the wait state or during the wait state // WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high // Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. // BURSTEN: Burst enable // Enables the burst access mode for the memory. Valid only with synchronous burst memories. // FACCEN: Flash access enable // Enables NOR Flash memory access operations. // MWID: Memory databus width <0=>8 bits <1=>16 bits // Defines the external memory device width, valid for all type of memories. // MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash // Defines the type of external memory attached to the corresponding memory bank. // MUXEN: Address/data multiplexing enable // When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. // MBKEN: Memory bank enable // Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a // disabled bank causes an ERROR on AHB bus. #define RTE_FSMC_BCR1_CBURSTRW 0 #define RTE_FSMC_BCR1_ASYNCWAIT 0 #define RTE_FSMC_BCR1_EXTMOD 0 #define RTE_FSMC_BCR1_WAITEN 1 #define RTE_FSMC_BCR1_WREN 1 #define RTE_FSMC_BCR1_WAITCFG 0 #define RTE_FSMC_BCR1_WRAPMOD 0 #define RTE_FSMC_BCR1_WAITPOL 0 #define RTE_FSMC_BCR1_BURSTEN 0 #define RTE_FSMC_BCR1_FACCEN 1 #define RTE_FSMC_BCR1_MWID 1 #define RTE_FSMC_BCR1_MTYP 2 #define RTE_FSMC_BCR1_MUXEN 1 #define RTE_FSMC_BCR1_MBKEN 1 // // Chip-select timing // ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D // Specifies the asynchronous access modes. Access mode is taken into account only when // Extended mode is enabled in the Chip-select control register. // DATLAT: Data latency <0-15> // For NOR Flash with synchronous burst mode enabled, defines the number of memory clock // cycles (+2) to issue to the memory before getting the first data: // 0000: Data latency of 2 CLK clock cycles for first burst access // 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) // Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) // periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. // In the case of CRAM, this field must be set to �0�. // CLKDIV: Clock divide ratio (for CLK signal) <1-15> // Defines the period of CLK clock output signal, expressed in number of HCLK cycles: // 0000: Reserved // 0001: CLK period = 2 � HCLK periods // 0010: CLK period = 3 � HCLK periods // 1111: CLK period = 16 � HCLK periods (default value after reset) // In asynchronous NOR Flash, SRAM or ROM accesses, this value is don�t care. // BUSTURN: Bus turnaround phase duration <0-15> // Define the bus turnaround delay after a read access only // from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive // addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the // minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the // databus in Hi-Z state. // These bits are written by software to add a delay at the end of a write/read transaction. This // delay allows to match the minimum time between consecutive transactions (tEHEL from NEx // high to NEx low) and the maximum time needed by the memory to free the data bus after a // read access (tEHQZ): // (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if // EXTMOD = �0� // (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = �1�. // 0000: BUSTURN phase duration = 0 HCLK clock cycle added // ... // 1111: BUSTURN phase duration = 15 � HCLK clock cycles (default value after reset) // DATAST: Data phase duration <1-255> // Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. // 0000 0000: Reserved // 0000 0001: DATAST phase duration = 1 � HCLK clock cycles // 0000 0010: DATAST phase duration = 2 � HCLK clock cycles // ... // 1111 1111: DATAST phase duration = 255 � HCLK clock cycles (default value after reset) // Note: In synchronous accesses, this value is don't care. // ADDHLD: Address hold phase duration <1-15> // Define the duration of the address hold phase used in mode D and multiplexed accesses. // 0000: Reserved // 0001: ADDHLD phase duration =1 � HCLK clock cycle // 0010: ADDHLD phase duration = 2 � HCLK clock cycle // ... // 1111: ADDHLD phase duration = 15 � HCLK clock cycles (default value after reset) // Note: In synchronous accesses, this value is not used, the address hold phase is always 1 // memory clock period duration. // ADDSET: Address setup phase duration <0-15> // Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. // 0000: ADDSET phase duration = 0 � HCLK clock cycle // ... // 1111: ADDSET phase duration = 1615 � HCLK clock cycles (default value after reset) // Note: In synchronous accesses, this value is don�t care. #define RTE_FSMC_BTR1_ACCMOD 0 #define RTE_FSMC_BTR1_DATLAT 15 #define RTE_FSMC_BTR1_CLKDIV 15 #define RTE_FSMC_BTR1_BUSTURN 15 #define RTE_FSMC_BTR1_DATAST 255 #define RTE_FSMC_BTR1_ADDHLD 15 #define RTE_FSMC_BTR1_ADDSET 15 // // Write timing // ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D // Specifies the asynchronous access modes. Access mode is taken into account only when // Extended mode is enabled in the Chip-select control register. // DATLAT: Data latency <0-15> // For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles // (+2) to issue to the memory before getting the first data. // 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access // ... // 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) // Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In // asynchronous NOR Flash, SRAM or ROM accesses, this value is don�t care. In case of // CRAM, this field must be set to 0 // CLKDIV: Clock divide ratio (for CLK signal) <1-15> // Defines the period of CLK clock output signal, expressed in number of HCLK cycles. // 0000: Reserved // 0001 CLK period = 2 � HCLK periods // 0010 CLK period = 3 � HCLK periods // 1111: CLK period = 16 � HCLK periods (default value after reset) // In asynchronous NOR Flash, SRAM or ROM accesses, this value is don�t care. // BUSTURN: Bus turnaround phase duration <0-15> // Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). // (BUSTRUN + 1) HCLK period = tEHELmin. // 0000: BUSTURN phase duration = 0 HCLK clock cycle added // ... // 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) // DATAST: Data phase duration <1-255> // Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. // 0000 0000: Reserved // 0000 0001: DATAST phase duration = 1 � HCLK clock cycles // 0000 0010: DATAST phase duration = 2 � HCLK clock cycles // ... // 1111 1111: DATAST phase duration = 255 � HCLK clock cycles (default value after reset) // Note: In synchronous accesses, this value is don't care. // ADDHLD: Address hold phase duration <1-15> // Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. // 0000: Reserved // 0001: ADDHLD phase duration = 1 � HCLK clock cycle // 0010: ADDHLD phase duration = 2 � HCLK clock cycle // ... // 1111: ADDHLD phase duration = 15 � HCLK clock cycles (default value after reset) // Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. // ADDSET: Address setup phase duration <1-15> // Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. // 0000: ADDSET phase duration = 0 � HCLK clock cycle // ... // 1111: ADDSET phase duration = 15 � HCLK clock cycles (default value after reset) // Note: In synchronous NOR Flash accesses, this value is don�t care. #define RTE_FSMC_BWTR1_ACCMOD 0 #define RTE_FSMC_BWTR1_DATLAT 15 #define RTE_FSMC_BWTR1_CLKDIV 15 #define RTE_FSMC_BWTR1_BUSTURN 15 #define RTE_FSMC_BWTR1_DATAST 255 #define RTE_FSMC_BWTR1_ADDHLD 15 #define RTE_FSMC_BWTR1_ADDSET 15 // // // FSMC_NE2 Chip Select // Configure Device on Chip Select FSMC_NE2 #define RTE_FSMC_NE2 0 // Chip-select control // CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write // For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash // memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. // ASYNCWAIT: Wait signal during asynchronous transfer // Enables the FSMC to use the wait signal even during an asynchronous protocol. // EXTMOD: Extended mode enable // Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. // WAITEN: Wait enable // For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. // WREN: Write enable // Enable/disable write operations in the current bank by the FSMC // WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state // For memory access in burst mode, the NWAIT signal indicates whether the data from the memory // are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted // by the memory one clock cycle before the wait state or during the wait state // WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high // Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. // BURSTEN: Burst enable // Enables the burst access mode for the memory. Valid only with synchronous burst memories. // FACCEN: Flash access enable // Enables NOR Flash memory access operations. // MWID: Memory databus width <0=>8 bits <1=>16 bits // Defines the external memory device width, valid for all type of memories. // MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash // Defines the type of external memory attached to the corresponding memory bank. // MUXEN: Address/data multiplexing enable // When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. // MBKEN: Memory bank enable // Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a // disabled bank causes an ERROR on AHB bus. #define RTE_FSMC_BCR2_CBURSTRW 0 #define RTE_FSMC_BCR2_ASYNCWAIT 0 #define RTE_FSMC_BCR2_EXTMOD 0 #define RTE_FSMC_BCR2_WAITEN 1 #define RTE_FSMC_BCR2_WREN 1 #define RTE_FSMC_BCR2_WAITCFG 0 #define RTE_FSMC_BCR2_WRAPMOD 0 #define RTE_FSMC_BCR2_WAITPOL 0 #define RTE_FSMC_BCR2_BURSTEN 0 #define RTE_FSMC_BCR2_FACCEN 1 #define RTE_FSMC_BCR2_MWID 1 #define RTE_FSMC_BCR2_MTYP 0 #define RTE_FSMC_BCR2_MUXEN 1 #define RTE_FSMC_BCR2_MBKEN 0 // // Chip-select timing // ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D // Specifies the asynchronous access modes. Access mode is taken into account only when // Extended mode is enabled in the Chip-select control register. // DATLAT: Data latency <0-15> // For NOR Flash with synchronous burst mode enabled, defines the number of memory clock // cycles (+2) to issue to the memory before getting the first data: // 0000: Data latency of 2 CLK clock cycles for first burst access // 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) // Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) // periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. // In the case of CRAM, this field must be set to �0�. // CLKDIV: Clock divide ratio (for CLK signal) <1-15> // Defines the period of CLK clock output signal, expressed in number of HCLK cycles: // 0000: Reserved // 0001: CLK period = 2 � HCLK periods // 0010: CLK period = 3 � HCLK periods // 1111: CLK period = 16 � HCLK periods (default value after reset) // In asynchronous NOR Flash, SRAM or ROM accesses, this value is don�t care. // BUSTURN: Bus turnaround phase duration <0-15> // Define the bus turnaround delay after a read access only // from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive // addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the // minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the // databus in Hi-Z state. // These bits are written by software to add a delay at the end of a write/read transaction. This // delay allows to match the minimum time between consecutive transactions (tEHEL from NEx // high to NEx low) and the maximum time needed by the memory to free the data bus after a // read access (tEHQZ): // (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if // EXTMOD = �0� // (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = �1�. // 0000: BUSTURN phase duration = 0 HCLK clock cycle added // ... // 1111: BUSTURN phase duration = 15 � HCLK clock cycles (default value after reset) // DATAST: Data phase duration <1-255> // Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. // 0000 0000: Reserved // 0000 0001: DATAST phase duration = 1 � HCLK clock cycles // 0000 0010: DATAST phase duration = 2 � HCLK clock cycles // ... // 1111 1111: DATAST phase duration = 255 � HCLK clock cycles (default value after reset) // Note: In synchronous accesses, this value is don't care. // ADDHLD: Address hold phase duration <1-15> // Define the duration of the address hold phase used in mode D and multiplexed accesses. // 0000: Reserved // 0001: ADDHLD phase duration =1 � HCLK clock cycle // 0010: ADDHLD phase duration = 2 � HCLK clock cycle // ... // 1111: ADDHLD phase duration = 15 � HCLK clock cycles (default value after reset) // Note: In synchronous accesses, this value is not used, the address hold phase is always 1 // memory clock period duration. // ADDSET: Address setup phase duration <0-15> // Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. // 0000: ADDSET phase duration = 0 � HCLK clock cycle // ... // 1111: ADDSET phase duration = 1615 � HCLK clock cycles (default value after reset) // Note: In synchronous accesses, this value is don�t care. #define RTE_FSMC_BTR2_ACCMOD 0 #define RTE_FSMC_BTR2_DATLAT 15 #define RTE_FSMC_BTR2_CLKDIV 15 #define RTE_FSMC_BTR2_BUSTURN 15 #define RTE_FSMC_BTR2_DATAST 255 #define RTE_FSMC_BTR2_ADDHLD 15 #define RTE_FSMC_BTR2_ADDSET 15 // // Write timing // ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D // Specifies the asynchronous access modes. Access mode is taken into account only when // Extended mode is enabled in the Chip-select control register. // DATLAT: Data latency <0-15> // For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles // (+2) to issue to the memory before getting the first data. // 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access // ... // 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) // Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In // asynchronous NOR Flash, SRAM or ROM accesses, this value is don�t care. In case of // CRAM, this field must be set to 0 // CLKDIV: Clock divide ratio (for CLK signal) <1-15> // Defines the period of CLK clock output signal, expressed in number of HCLK cycles. // 0000: Reserved // 0001 CLK period = 2 � HCLK periods // 0010 CLK period = 3 � HCLK periods // 1111: CLK period = 16 � HCLK periods (default value after reset) // In asynchronous NOR Flash, SRAM or ROM accesses, this value is don�t care. // BUSTURN: Bus turnaround phase duration <0-15> // Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). // (BUSTRUN + 1) HCLK period = tEHELmin. // 0000: BUSTURN phase duration = 0 HCLK clock cycle added // ... // 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) // DATAST: Data phase duration <1-255> // Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. // 0000 0000: Reserved // 0000 0001: DATAST phase duration = 1 � HCLK clock cycles // 0000 0010: DATAST phase duration = 2 � HCLK clock cycles // ... // 1111 1111: DATAST phase duration = 255 � HCLK clock cycles (default value after reset) // Note: In synchronous accesses, this value is don't care. // ADDHLD: Address hold phase duration <1-15> // Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. // 0000: Reserved // 0001: ADDHLD phase duration = 1 � HCLK clock cycle // 0010: ADDHLD phase duration = 2 � HCLK clock cycle // ... // 1111: ADDHLD phase duration = 15 � HCLK clock cycles (default value after reset) // Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. // ADDSET: Address setup phase duration <1-15> // Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. // 0000: ADDSET phase duration = 0 � HCLK clock cycle // ... // 1111: ADDSET phase duration = 15 � HCLK clock cycles (default value after reset) // Note: In synchronous NOR Flash accesses, this value is don�t care. #define RTE_FSMC_BWTR2_ACCMOD 0 #define RTE_FSMC_BWTR2_DATLAT 15 #define RTE_FSMC_BWTR2_CLKDIV 15 #define RTE_FSMC_BWTR2_BUSTURN 15 #define RTE_FSMC_BWTR2_DATAST 255 #define RTE_FSMC_BWTR2_ADDHLD 15 #define RTE_FSMC_BWTR2_ADDSET 15 // // // FSMC_NE3 Chip Select // Configure Device on Chip Select FSMC_NE3 #define RTE_FSMC_NE3 0 // Chip-select control // CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write // For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash // memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. // ASYNCWAIT: Wait signal during asynchronous transfer // Enables the FSMC to use the wait signal even during an asynchronous protocol. // EXTMOD: Extended mode enable // Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. // WAITEN: Wait enable // For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. // WREN: Write enable // Enable/disable write operations in the current bank by the FSMC // WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state // For memory access in burst mode, the NWAIT signal indicates whether the data from the memory // are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted // by the memory one clock cycle before the wait state or during the wait state // WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high // Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. // BURSTEN: Burst enable // Enables the burst access mode for the memory. Valid only with synchronous burst memories. // FACCEN: Flash access enable // Enables NOR Flash memory access operations. // MWID: Memory databus width <0=>8 bits <1=>16 bits // Defines the external memory device width, valid for all type of memories. // MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash // Defines the type of external memory attached to the corresponding memory bank. // MUXEN: Address/data multiplexing enable // When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. // MBKEN: Memory bank enable // Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a // disabled bank causes an ERROR on AHB bus. #define RTE_FSMC_BCR3_CBURSTRW 0 #define RTE_FSMC_BCR3_ASYNCWAIT 0 #define RTE_FSMC_BCR3_EXTMOD 0 #define RTE_FSMC_BCR3_WAITEN 1 #define RTE_FSMC_BCR3_WREN 1 #define RTE_FSMC_BCR3_WAITCFG 0 #define RTE_FSMC_BCR3_WRAPMOD 0 #define RTE_FSMC_BCR3_WAITPOL 0 #define RTE_FSMC_BCR3_BURSTEN 0 #define RTE_FSMC_BCR3_FACCEN 1 #define RTE_FSMC_BCR3_MWID 1 #define RTE_FSMC_BCR3_MTYP 0 #define RTE_FSMC_BCR3_MUXEN 1 #define RTE_FSMC_BCR3_MBKEN 0 // // Chip-select timing // ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D // Specifies the asynchronous access modes. Access mode is taken into account only when // Extended mode is enabled in the Chip-select control register. // DATLAT: Data latency <0-15> // For NOR Flash with synchronous burst mode enabled, defines the number of memory clock // cycles (+2) to issue to the memory before getting the first data: // 0000: Data latency of 2 CLK clock cycles for first burst access // 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) // Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) // periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. // In the case of CRAM, this field must be set to �0�. // CLKDIV: Clock divide ratio (for CLK signal) <1-15> // Defines the period of CLK clock output signal, expressed in number of HCLK cycles: // 0000: Reserved // 0001: CLK period = 2 � HCLK periods // 0010: CLK period = 3 � HCLK periods // 1111: CLK period = 16 � HCLK periods (default value after reset) // In asynchronous NOR Flash, SRAM or ROM accesses, this value is don�t care. // BUSTURN: Bus turnaround phase duration <0-15> // Define the bus turnaround delay after a read access only // from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive // addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the // minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the // databus in Hi-Z state. // These bits are written by software to add a delay at the end of a write/read transaction. This // delay allows to match the minimum time between consecutive transactions (tEHEL from NEx // high to NEx low) and the maximum time needed by the memory to free the data bus after a // read access (tEHQZ): // (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if // EXTMOD = �0� // (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = �1�. // 0000: BUSTURN phase duration = 0 HCLK clock cycle added // ... // 1111: BUSTURN phase duration = 15 � HCLK clock cycles (default value after reset) // DATAST: Data phase duration <1-255> // Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. // 0000 0000: Reserved // 0000 0001: DATAST phase duration = 1 � HCLK clock cycles // 0000 0010: DATAST phase duration = 2 � HCLK clock cycles // ... // 1111 1111: DATAST phase duration = 255 � HCLK clock cycles (default value after reset) // Note: In synchronous accesses, this value is don't care. // ADDHLD: Address hold phase duration <1-15> // Define the duration of the address hold phase used in mode D and multiplexed accesses. // 0000: Reserved // 0001: ADDHLD phase duration =1 � HCLK clock cycle // 0010: ADDHLD phase duration = 2 � HCLK clock cycle // ... // 1111: ADDHLD phase duration = 15 � HCLK clock cycles (default value after reset) // Note: In synchronous accesses, this value is not used, the address hold phase is always 1 // memory clock period duration. // ADDSET: Address setup phase duration <0-15> // Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. // 0000: ADDSET phase duration = 0 � HCLK clock cycle // ... // 1111: ADDSET phase duration = 1615 � HCLK clock cycles (default value after reset) // Note: In synchronous accesses, this value is don�t care. #define RTE_FSMC_BTR3_ACCMOD 0 #define RTE_FSMC_BTR3_DATLAT 15 #define RTE_FSMC_BTR3_CLKDIV 15 #define RTE_FSMC_BTR3_BUSTURN 15 #define RTE_FSMC_BTR3_DATAST 255 #define RTE_FSMC_BTR3_ADDHLD 15 #define RTE_FSMC_BTR3_ADDSET 15 // // Write timing // ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D // Specifies the asynchronous access modes. Access mode is taken into account only when // Extended mode is enabled in the Chip-select control register. // DATLAT: Data latency <0-15> // For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles // (+2) to issue to the memory before getting the first data. // 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access // ... // 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) // Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In // asynchronous NOR Flash, SRAM or ROM accesses, this value is don�t care. In case of // CRAM, this field must be set to 0 // CLKDIV: Clock divide ratio (for CLK signal) <1-15> // Defines the period of CLK clock output signal, expressed in number of HCLK cycles. // 0000: Reserved // 0001 CLK period = 2 � HCLK periods // 0010 CLK period = 3 � HCLK periods // 1111: CLK period = 16 � HCLK periods (default value after reset) // In asynchronous NOR Flash, SRAM or ROM accesses, this value is don�t care. // BUSTURN: Bus turnaround phase duration <0-15> // Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). // (BUSTRUN + 1) HCLK period = tEHELmin. // 0000: BUSTURN phase duration = 0 HCLK clock cycle added // ... // 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) // DATAST: Data phase duration <1-255> // Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. // 0000 0000: Reserved // 0000 0001: DATAST phase duration = 1 � HCLK clock cycles // 0000 0010: DATAST phase duration = 2 � HCLK clock cycles // ... // 1111 1111: DATAST phase duration = 255 � HCLK clock cycles (default value after reset) // Note: In synchronous accesses, this value is don't care. // ADDHLD: Address hold phase duration <1-15> // Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. // 0000: Reserved // 0001: ADDHLD phase duration = 1 � HCLK clock cycle // 0010: ADDHLD phase duration = 2 � HCLK clock cycle // ... // 1111: ADDHLD phase duration = 15 � HCLK clock cycles (default value after reset) // Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. // ADDSET: Address setup phase duration <1-15> // Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. // 0000: ADDSET phase duration = 0 � HCLK clock cycle // ... // 1111: ADDSET phase duration = 15 � HCLK clock cycles (default value after reset) // Note: In synchronous NOR Flash accesses, this value is don�t care. #define RTE_FSMC_BWTR3_ACCMOD 0 #define RTE_FSMC_BWTR3_DATLAT 15 #define RTE_FSMC_BWTR3_CLKDIV 15 #define RTE_FSMC_BWTR3_BUSTURN 15 #define RTE_FSMC_BWTR3_DATAST 255 #define RTE_FSMC_BWTR3_ADDHLD 15 #define RTE_FSMC_BWTR3_ADDSET 15 // // // FSMC_NE4 Chip Select // Configure Device on Chip Select FSMC_NE4 #define RTE_FSMC_NE4 0 // Chip-select control // CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write // For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash // memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. // ASYNCWAIT: Wait signal during asynchronous transfer // Enables the FSMC to use the wait signal even during an asynchronous protocol. // EXTMOD: Extended mode enable // Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. // WAITEN: Wait enable // For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. // WREN: Write enable // Enable/disable write operations in the current bank by the FSMC // WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state // For memory access in burst mode, the NWAIT signal indicates whether the data from the memory // are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted // by the memory one clock cycle before the wait state or during the wait state // WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high // Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. // BURSTEN: Burst enable // Enables the burst access mode for the memory. Valid only with synchronous burst memories. // FACCEN: Flash access enable // Enables NOR Flash memory access operations. // MWID: Memory databus width <0=>8 bits <1=>16 bits // Defines the external memory device width, valid for all type of memories. // MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash // Defines the type of external memory attached to the corresponding memory bank. // MUXEN: Address/data multiplexing enable // When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. // MBKEN: Memory bank enable // Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a // disabled bank causes an ERROR on AHB bus. #define RTE_FSMC_BCR4_CBURSTRW 0 #define RTE_FSMC_BCR4_ASYNCWAIT 0 #define RTE_FSMC_BCR4_EXTMOD 0 #define RTE_FSMC_BCR4_WAITEN 1 #define RTE_FSMC_BCR4_WREN 1 #define RTE_FSMC_BCR4_WAITCFG 0 #define RTE_FSMC_BCR4_WRAPMOD 0 #define RTE_FSMC_BCR4_WAITPOL 0 #define RTE_FSMC_BCR4_BURSTEN 0 #define RTE_FSMC_BCR4_FACCEN 1 #define RTE_FSMC_BCR4_MWID 1 #define RTE_FSMC_BCR4_MTYP 0 #define RTE_FSMC_BCR4_MUXEN 1 #define RTE_FSMC_BCR4_MBKEN 0 // // Chip-select timing // ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D // Specifies the asynchronous access modes. Access mode is taken into account only when // Extended mode is enabled in the Chip-select control register. // DATLAT: Data latency <0-15> // For NOR Flash with synchronous burst mode enabled, defines the number of memory clock // cycles (+2) to issue to the memory before getting the first data: // 0000: Data latency of 2 CLK clock cycles for first burst access // 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) // Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) // periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. // In the case of CRAM, this field must be set to �0�. // CLKDIV: Clock divide ratio (for CLK signal) <1-15> // Defines the period of CLK clock output signal, expressed in number of HCLK cycles: // 0000: Reserved // 0001: CLK period = 2 � HCLK periods // 0010: CLK period = 3 � HCLK periods // 1111: CLK period = 16 � HCLK periods (default value after reset) // In asynchronous NOR Flash, SRAM or ROM accesses, this value is don�t care. // BUSTURN: Bus turnaround phase duration <0-15> // Define the bus turnaround delay after a read access only // from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive // addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the // minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the // databus in Hi-Z state. // These bits are written by software to add a delay at the end of a write/read transaction. This // delay allows to match the minimum time between consecutive transactions (tEHEL from NEx // high to NEx low) and the maximum time needed by the memory to free the data bus after a // read access (tEHQZ): // (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if // EXTMOD = �0� // (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = �1�. // 0000: BUSTURN phase duration = 0 HCLK clock cycle added // ... // 1111: BUSTURN phase duration = 15 � HCLK clock cycles (default value after reset) // DATAST: Data phase duration <1-255> // Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. // 0000 0000: Reserved // 0000 0001: DATAST phase duration = 1 � HCLK clock cycles // 0000 0010: DATAST phase duration = 2 � HCLK clock cycles // ... // 1111 1111: DATAST phase duration = 255 � HCLK clock cycles (default value after reset) // Note: In synchronous accesses, this value is don't care. // ADDHLD: Address hold phase duration <1-15> // Define the duration of the address hold phase used in mode D and multiplexed accesses. // 0000: Reserved // 0001: ADDHLD phase duration =1 � HCLK clock cycle // 0010: ADDHLD phase duration = 2 � HCLK clock cycle // ... // 1111: ADDHLD phase duration = 15 � HCLK clock cycles (default value after reset) // Note: In synchronous accesses, this value is not used, the address hold phase is always 1 // memory clock period duration. // ADDSET: Address setup phase duration <0-15> // Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. // 0000: ADDSET phase duration = 0 � HCLK clock cycle // ... // 1111: ADDSET phase duration = 1615 � HCLK clock cycles (default value after reset) // Note: In synchronous accesses, this value is don�t care. #define RTE_FSMC_BTR4_ACCMOD 0 #define RTE_FSMC_BTR4_DATLAT 15 #define RTE_FSMC_BTR4_CLKDIV 15 #define RTE_FSMC_BTR4_BUSTURN 15 #define RTE_FSMC_BTR4_DATAST 255 #define RTE_FSMC_BTR4_ADDHLD 15 #define RTE_FSMC_BTR4_ADDSET 15 // // Write timing // ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D // Specifies the asynchronous access modes. Access mode is taken into account only when // Extended mode is enabled in the Chip-select control register. // DATLAT: Data latency <0-15> // For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles // (+2) to issue to the memory before getting the first data. // 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access // ... // 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) // Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In // asynchronous NOR Flash, SRAM or ROM accesses, this value is don�t care. In case of // CRAM, this field must be set to 0 // CLKDIV: Clock divide ratio (for CLK signal) <1-15> // Defines the period of CLK clock output signal, expressed in number of HCLK cycles. // 0000: Reserved // 0001 CLK period = 2 � HCLK periods // 0010 CLK period = 3 � HCLK periods // 1111: CLK period = 16 � HCLK periods (default value after reset) // In asynchronous NOR Flash, SRAM or ROM accesses, this value is don�t care. // BUSTURN: Bus turnaround phase duration <0-15> // Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). // (BUSTRUN + 1) HCLK period = tEHELmin. // 0000: BUSTURN phase duration = 0 HCLK clock cycle added // ... // 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) // DATAST: Data phase duration <1-255> // Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. // 0000 0000: Reserved // 0000 0001: DATAST phase duration = 1 � HCLK clock cycles // 0000 0010: DATAST phase duration = 2 � HCLK clock cycles // ... // 1111 1111: DATAST phase duration = 255 � HCLK clock cycles (default value after reset) // Note: In synchronous accesses, this value is don't care. // ADDHLD: Address hold phase duration <1-15> // Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. // 0000: Reserved // 0001: ADDHLD phase duration = 1 � HCLK clock cycle // 0010: ADDHLD phase duration = 2 � HCLK clock cycle // ... // 1111: ADDHLD phase duration = 15 � HCLK clock cycles (default value after reset) // Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. // ADDSET: Address setup phase duration <1-15> // Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. // 0000: ADDSET phase duration = 0 � HCLK clock cycle // ... // 1111: ADDSET phase duration = 15 � HCLK clock cycles (default value after reset) // Note: In synchronous NOR Flash accesses, this value is don�t care. #define RTE_FSMC_BWTR4_ACCMOD 0 #define RTE_FSMC_BWTR4_DATLAT 15 #define RTE_FSMC_BWTR4_CLKDIV 15 #define RTE_FSMC_BWTR4_BUSTURN 15 #define RTE_FSMC_BWTR4_DATAST 255 #define RTE_FSMC_BWTR4_ADDHLD 15 #define RTE_FSMC_BWTR4_ADDSET 15 // // // // NAND Flash Controller // FSMC_NCE2 Chip Select // Configure NAND Device on Chip Select FSMC_NCE2 #define RTE_FSMC_NCE2 0 // NAND Flash Control // ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes // Defines the page size for the extended ECC. // TAR: ALE to RE delay <0-15> // Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). // Time is: t_ar = (TAR + SET + 2) � THCLK where THCLK is the HCLK clock period // 0000: 1 HCLK cycle (default) // 1111: 16 HCLK cycles // Note: SET is MEMSET or ATTSET according to the addressed space. // TCLR: CLE to RE delay <0-15> // Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). // Time is t_clr = (TCLR + SET + 2) � THCLK where THCLK is the HCLK clock period // 0000: 1 HCLK cycle (default) // 1111: 16 HCLK cycles // Note: SET is MEMSET or ATTSET according to the addressed space. // ECCEN: ECC computation logic enable // PWID: Databus width <0=>8 bits <1=>16 bits // Defines the external memory device width. // PTYP: Memory type <1=>NAND Flash // Defines the type of device attached to the corresponding memory bank. // PBKEN: NAND Flash memory bank enable // Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. // PWAITEN: Wait feature enable // Enables the Wait feature for the PC Card/NAND Flash memory bank. #define RTE_FSMC_PCR2_ECCPS 0 #define RTE_FSMC_PCR2_TAR 0 #define RTE_FSMC_PCR2_TCLR 0 #define RTE_FSMC_PCR2_ECCEN 0 #define RTE_FSMC_PCR2_PWID 0 #define RTE_FSMC_PCR2_PTYP 1 #define RTE_FSMC_PCR2_PBKEN 0 #define RTE_FSMC_PCR2_PWAITEN 0 // // Interrupt configuration // IFEN: Falling edge detection enable // ILEN: High-level detection enable // IREN: Rising edge detection enable #define RTE_FSMC_SR2_IFEN 0 #define RTE_FSMC_SR2_ILEN 0 #define RTE_FSMC_SR2_IREN 0 // // Common memory space timing // MEMHIZ: Databus HiZ time <0-255> // Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the // start of a NAND Flash write access. // 0000 0000: 0 HCLK cycle // 1111 1111: 255 HCLK cycles (default value after reset) // MEMHOLD: Hold time <1-255> // Defines the number of HCLK clock cycles to hold address (and data for write access) after // the command deassertion (NWE, NOE), for NAND Flash read or write access. // 0000 0000: reserved // 0000 0001: 1 HCLK cycle // 1111 1111: 255 HCLK cycles (default value after reset) // MEMWAIT: Wait time <1-255> // Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, // NOE), for NAND Flash read or write access to. The duration for command assertion // is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. // 0000 0000: reserved // 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) // 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) // MEMSET: Setup time <0-255> // Defines the number of HCLK (+1) clock cycles to set up the address before the command // assertion (NWE, NOE), for NAND Flash read or write access. // 0000 0000: 2 HCLK cycles (for NAND Flash) // 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) #define RTE_FSMC_PMEM2_MEMHIZ 255 #define RTE_FSMC_PMEM2_MEMHOLD 255 #define RTE_FSMC_PMEM2_MEMWAIT 255 #define RTE_FSMC_PMEM2_MEMSET 255 // // Attribute memory space timing // ATTHIZ: Databus HiZ time <0-255> // Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the // start of a NAND Flash write access. // 0000 0000: 0 HCLK cycle // 1111 1111: 255 HCLK cycles (default value after reset) // ATTHOLD: Hold time <1-255> // Defines the number of HCLK clock cycles to hold address (and data for write access) after // the command deassertion (NWE, NOE), for NAND Flash read or write access. // 0000 0000: reserved // 0000 0001: 1 HCLK cycle // 1111 1111: 255 HCLK cycles (default value after reset) // ATTWAIT: Wait time <1-255> // Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, // NOE), for NAND Flash read or write access. The duration for command assertion // is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. // 0000 0000: reserved // 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) // 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) // ATTSET: Setup time <0-255> // Defines the number of HCLK (+1) clock cycles to set up address before the command // assertion (NWE, NOE), for NAND Flash read or write access. // 0000 0000: 1 HCLK cycle // 1111 1111: 256 HCLK cycles (default value after reset) #define RTE_FSMC_PATT2_ATTHIZ 255 #define RTE_FSMC_PATT2_ATTHOLD 255 #define RTE_FSMC_PATT2_ATTWAIT 255 #define RTE_FSMC_PATT2_ATTSET 255 // // // FSMC_NCE3 Chip Select // Configure NAND Device on Chip Select FSMC_NCE3 #define RTE_FSMC_NCE3 0 // NAND Flash Control // ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes // Defines the page size for the extended ECC. // TAR: ALE to RE delay <0-15> // Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). // Time is: t_ar = (TAR + SET + 2) � THCLK where THCLK is the HCLK clock period // 0000: 1 HCLK cycle (default) // 1111: 16 HCLK cycles // Note: SET is MEMSET or ATTSET according to the addressed space. // TCLR: CLE to RE delay <0-15> // Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). // Time is t_clr = (TCLR + SET + 2) � THCLK where THCLK is the HCLK clock period // 0000: 1 HCLK cycle (default) // 1111: 16 HCLK cycles // Note: SET is MEMSET or ATTSET according to the addressed space. // ECCEN: ECC computation logic enable // PWID: Databus width <0=>8 bits <1=>16 bits // Defines the external memory device width. // PTYP: Memory type <1=>NAND Flash // Defines the type of device attached to the corresponding memory bank. // PBKEN: NAND Flash memory bank enable // Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. // PWAITEN: Wait feature enable // Enables the Wait feature for the PC Card/NAND Flash memory bank. #define RTE_FSMC_PCR3_ECCPS 0 #define RTE_FSMC_PCR3_TAR 0 #define RTE_FSMC_PCR3_TCLR 0 #define RTE_FSMC_PCR3_ECCEN 0 #define RTE_FSMC_PCR3_PWID 0 #define RTE_FSMC_PCR3_PTYP 1 #define RTE_FSMC_PCR3_PBKEN 0 #define RTE_FSMC_PCR3_PWAITEN 0 // // Interrupt configuration // IFEN: Falling edge detection enable // ILEN: High-level detection enable // IREN: Rising edge detection enable #define RTE_FSMC_SR3_IFEN 0 #define RTE_FSMC_SR3_ILEN 0 #define RTE_FSMC_SR3_IREN 0 // // Common memory space timing // MEMHIZ: Databus HiZ time <0-255> // Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the // start of a NAND Flash write access. // 0000 0000: 0 HCLK cycle // 1111 1111: 255 HCLK cycles (default value after reset) // MEMHOLD: Hold time <1-255> // Defines the number of HCLK clock cycles to hold address (and data for write access) after // the command deassertion (NWE, NOE), for NAND Flash read or write access. // 0000 0000: reserved // 0000 0001: 1 HCLK cycle // 1111 1111: 255 HCLK cycles (default value after reset) // MEMWAIT: Wait time <1-255> // Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, // NOE), for NAND Flash read or write access to. The duration for command assertion // is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. // 0000 0000: reserved // 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) // 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) // MEMSET: Setup time <0-255> // Defines the number of HCLK (+1) clock cycles to set up the address before the command // assertion (NWE, NOE), for NAND Flash read or write access. // 0000 0000: 2 HCLK cycles (for NAND Flash) // 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) #define RTE_FSMC_PMEM3_MEMHIZ 255 #define RTE_FSMC_PMEM3_MEMHOLD 255 #define RTE_FSMC_PMEM3_MEMWAIT 255 #define RTE_FSMC_PMEM3_MEMSET 255 // // Attribute memory space timing // ATTHIZ: Databus HiZ time <0-255> // Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the // start of a NAND Flash write access. // 0000 0000: 0 HCLK cycle // 1111 1111: 255 HCLK cycles (default value after reset) // ATTHOLD: Hold time <1-255> // Defines the number of HCLK clock cycles to hold address (and data for write access) after // the command deassertion (NWE, NOE), for NAND Flash read or write access. // 0000 0000: reserved // 0000 0001: 1 HCLK cycle // 1111 1111: 255 HCLK cycles (default value after reset) // ATTWAIT: Wait time <1-255> // Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, // NOE), for NAND Flash read or write access. The duration for command assertion // is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. // 0000 0000: reserved // 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) // 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) // ATTSET: Setup time <0-255> // Defines the number of HCLK (+1) clock cycles to set up address before the command // assertion (NWE, NOE), for NAND Flash read or write access. // 0000 0000: 1 HCLK cycle // 1111 1111: 256 HCLK cycles (default value after reset) #define RTE_FSMC_PATT3_ATTHIZ 255 #define RTE_FSMC_PATT3_ATTHOLD 255 #define RTE_FSMC_PATT3_ATTWAIT 255 #define RTE_FSMC_PATT3_ATTSET 255 // // // // PC Card Controller // FSMC_NCE4_x Chip Select // Configure PC Card/CompactFlash Device on Chip Select FSMC_NCE4_1/FSMC_NCE4_2 #define RTE_FSMC_NCE4 0 // PC Card Control // ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes // Defines the page size for the extended ECC. // TAR: ALE to RE delay <0-15> // Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). // Time is: t_ar = (TAR + SET + 2) � THCLK where THCLK is the HCLK clock period // 0000: 1 HCLK cycle (default) // 1111: 16 HCLK cycles // Note: SET is MEMSET or ATTSET according to the addressed space. // TCLR: CLE to RE delay <0-15> // Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). // Time is t_clr = (TCLR + SET + 2) � THCLK where THCLK is the HCLK clock period // 0000: 1 HCLK cycle (default) // 1111: 16 HCLK cycles // Note: SET is MEMSET or ATTSET according to the addressed space. // ECCEN: ECC computation logic enable // PWID: Databus width <0=>8 bits <1=>16 bits // Defines the external memory device width. // PTYP: Memory type <0=>PC Card, CompactFlash, CF+ or PCMCIOA // Defines the type of device attached to the corresponding memory bank. // PBKEN: PC Card memory bank enable // Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. // PWAITEN: Wait feature enable // Enables the Wait feature for the PC Card/NAND Flash memory bank. #define RTE_FSMC_PCR4_ECCPS 0 #define RTE_FSMC_PCR4_TAR 0 #define RTE_FSMC_PCR4_TCLR 0 #define RTE_FSMC_PCR4_ECCEN 0 #define RTE_FSMC_PCR4_PWID 0 #define RTE_FSMC_PCR4_PTYP 0 #define RTE_FSMC_PCR4_PBKEN 0 #define RTE_FSMC_PCR4_PWAITEN 0 // // Interrupt configuration // IFEN: Falling edge detection enable // ILEN: High-level detection enable // IREN: Rising edge detection enable #define RTE_FSMC_SR4_IFEN 0 #define RTE_FSMC_SR4_ILEN 0 #define RTE_FSMC_SR4_IREN 0 // // Common memory space timing // MEMHIZ: Databus HiZ time <0-255> // Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the // start of a NAND Flash write access. // 0000 0000: 0 HCLK cycle // 1111 1111: 255 HCLK cycles (default value after reset) // MEMHOLD: Hold time <1-255> // Defines the number of HCLK clock cycles to hold address (and data for write access) after // the command deassertion (NWE, NOE), for NAND Flash read or write access. // 0000 0000: reserved // 0000 0001: 1 HCLK cycle // 1111 1111: 255 HCLK cycles (default value after reset) // MEMWAIT: Wait time <1-255> // Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, // NOE), for NAND Flash read or write access to. The duration for command assertion // is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. // 0000 0000: reserved // 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) // 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) // MEMSET: Setup time <0-255> // Defines the number of HCLK (+1) clock cycles to set up the address before the command // assertion (NWE, NOE), for NAND Flash read or write access. // 0000 0000: 2 HCLK cycles (for NAND Flash) // 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) #define RTE_FSMC_PMEM4_MEMHIZ 255 #define RTE_FSMC_PMEM4_MEMHOLD 255 #define RTE_FSMC_PMEM4_MEMWAIT 255 #define RTE_FSMC_PMEM4_MEMSET 255 // // Attribute memory space timing // ATTHIZ: Databus HiZ time <0-255> // Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the // start of a NAND Flash write access. // 0000 0000: 0 HCLK cycle // 1111 1111: 255 HCLK cycles (default value after reset) // ATTHOLD: Hold time <1-255> // Defines the number of HCLK clock cycles to hold address (and data for write access) after // the command deassertion (NWE, NOE), for NAND Flash read or write access. // 0000 0000: reserved // 0000 0001: 1 HCLK cycle // 1111 1111: 255 HCLK cycles (default value after reset) // ATTWAIT: Wait time <1-255> // Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, // NOE), for NAND Flash read or write access. The duration for command assertion // is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. // 0000 0000: reserved // 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) // 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) // ATTSET: Setup time <0-255> // Defines the number of HCLK (+1) clock cycles to set up address before the command // assertion (NWE, NOE), for NAND Flash read or write access. // 0000 0000: 1 HCLK cycle // 1111 1111: 256 HCLK cycles (default value after reset) #define RTE_FSMC_PATT4_ATTHIZ 255 #define RTE_FSMC_PATT4_ATTHOLD 255 #define RTE_FSMC_PATT4_ATTWAIT 255 #define RTE_FSMC_PATT4_ATTSET 255 // // I/O space timing // IOHIZ: Databus HiZ time <0-255> // Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the // start of a PC Card write access. Only valid for write transaction. // 0000 0000: 0 HCLK cycle // 1111 1111: 255 HCLK cycles (default value after reset) // IOHOLD: Hold time <1-255> // Defines the number of HCLK clock cycles to hold address (and data for write access) after // the command deassertion (NWE, NOE), for PC Card read or write access. // 0000 0000: reserved // 0000 0001: 1 HCLK cycle // 1111 1111: 255 HCLK cycles (default value after reset) // IOWAIT: Wait time <1-255> // Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, // SMNOE), for PC Card read or write access. The duration for command assertion is // extended if the wait signal (NWAIT) is active (low) at the end of the // programmed value of HCLK. // 0000 0000: reserved, do not use this value // 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) // 1111 1111: 256 HCLK cycles // IOSET: Setup time <0-255> // Defines the number of HCLK (+1) clock cycles to set up the address before the command // assertion (NWE, NOE), for PC Card read or write access. // 0000 0000: 1 HCLK cycle // 1111 1111: 256 HCLK cycles (default value after reset) #define RTE_FSMC_PIO4_IOHIZ 255 #define RTE_FSMC_PIO4_IOHOLD 255 #define RTE_FSMC_PIO4_IOWAIT 255 #define RTE_FSMC_PIO4_IOSET 255 // // // // #endif /* __RTE_DEVICE_H */ [/#list] #n