NVIC

NVIC Nested Vectored Interrupt Controller The nested vector interrupt controller NVIC includes the following features: • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M4 with FPU) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214. NVIC Nested Vectored Interrupt Controller The nested vector interrupt controller NVIC includes the following features: • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M4 with FPU) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214. NVIC Nested Vectored Interrupt Controller The nested vector interrupt controller NVIC includes the following features: • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M4 with FPU) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214. NVIC Nested Vectored Interrupt Controller The nested vector interrupt controller NVIC includes the following features: • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M4 with FPU) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214. NVIC Nested Vectored Interrupt Controller The nested vector interrupt controller NVIC includes the following features: • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M4 with FPU) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214. NVIC Nested Vectored Interrupt Controller The nested vector interrupt controller NVIC includes the following features: • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M4 with FPU) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214. NVIC Nested Vectored Interrupt Controller The nested vector interrupt controller NVIC includes the following features: • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M4 with FPU) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214. NVIC Nested Vectored Interrupt Controller The nested vector interrupt controller NVIC includes the following features: • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M4 with FPU) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214. NVIC Nested Vectored Interrupt Controller The nested vector interrupt controller NVIC includes the following features: • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M4 with FPU) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214. NVIC Nested Vectored Interrupt Controller Both CPU1 (Cortex®-M7) and CPU2 (Cortex®-M4) cores have their own nested vector interrupt controller (respectively NVIC1 and NVIC2). The NVIC includes the following features: • up to 150 maskable interrupt channels for STM32H7xxx (not including the 16 interrupt lines of Cortex®-M7 / Cortex®-M4 with FPU) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to PM0253 and PM0214 programming manuals for Cortex®-M7 and for Cortex®-M4, respectively. NVIC Nested Vectored Interrupt Controller The nested vector interrupt controller NVIC includes the following features: • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M4 with FPU) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214. NVIC Nested Vectored Interrupt Controller The nested vector interrupt controller NVIC includes the following features: • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M4 with FPU) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214. NVIC Nested Vectored Interrupt Controller The nested vector interrupt controller NVIC includes the following features: • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M4 with FPU) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214. NVIC Nested Vectored Interrupt Controller The nested vector interrupt controller NVIC includes the following features: • 109 maskable interrupt channels (not including the 16 Cortex®-M33 with FPU interrupt lines) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. The NVIC registers are banked across secure and non-secure states. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214. NVIC Nested Vectored Interrupt Controller The nested vector interrupt controller NVIC includes the following features: • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M4 with FPU) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214. NVIC Nested Vectored Interrupt Controller The nested vector interrupt controller NVIC includes the following features: • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M4 with FPU) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214. NVIC Nested Vectored Interrupt Controller The nested vector interrupt controller NVIC includes the following features: CPU1 NVIC features: • 62 maskable interrupt channels (not including the sixteen Cortex®-M4 with DSP interrupt lines) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers CPU2 NVIC features: • 32 maskable interrupt channels (not including the sixteen Cortex®-M0+ interrupt lines) • Four programmable priority levels (two bits of interrupt priority used) • low-latency exception and interrupt handling • power management control The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information refer to the PM0214 programming manual for Cortex®-M4, and PM056 programming manual for Cortex®-M0+.