GTZC Global TrustZone® Controller

• TZSC: TrustZone® Security Controller

This sub-block defines the secure/privilege state of slave/master peripherals. It also

controls the non-secure area size for the WaterMark Memory Protection Controller

(MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about

the secure status of each securable peripheral, by sharing with RCC and I/O logic.

• MPCBB: Block-Based Memory Protection Controller

This sub-block controls secure states of all blocks (256-byte pages) of the associated SRAM.

• TZIC: TrustZone® Illegal access Controller

This sub-block gathers all illegal access events in the system and generates

a secure interrupt towards NVIC.


These sub-blocks are used to configure TrustZone® system security in a product having bus

agents with programmable-security and privileged attributes (securable) such as:

• on-chip RAM with programmable secure blocks (pages).

• AHB and APB peripherals with programmable security and/or privilege access.

• AHB master granted as secure and/or privilege.

• off-chip memories with secure areas.

]]> GTZC Global TrustZone® Controller

• TZSC: TrustZone® Security Controller

This sub-block defines the secure/privilege state of slave/master peripherals. It also

controls the non-secure area size for the WaterMark Memory Protection Controller

(MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about

the secure status of each securable peripheral, by sharing with RCC and I/O logic.

• MPCBB: Block-Based Memory Protection Controller

This sub-block controls secure states of all blocks (256-byte pages) of the associated SRAM.

• TZIC: TrustZone® Illegal access Controller

This sub-block gathers all illegal access events in the system and generates

a secure interrupt towards NVIC.


These sub-blocks are used to configure TrustZone® system security in a product having bus

agents with programmable-security and privileged attributes (securable) such as:

• on-chip RAM with programmable secure blocks (pages).

• AHB and APB peripherals with programmable security and/or privilege access.

• AHB master granted as secure and/or privilege.

• off-chip memories with secure areas.

]]> GTZC Global security Controller This section includes the description of the two following sub-blocks:

• TZSC (Security Controller):

This sub-block defines the secure/privileged state of secured slave peripherals. It also controls the unprivileged area size for the watermark memory peripheral controller (MPCWM).

• TZIC (Security Illegal access Controller):

This sub-block gathers all illegal access events in the system and generates a secure interrupt towards the secure CPU2 (CM0+) NVIC.

These sub-blocks are used to configure the system security and privilege such as:

• on-chip Flash memory and RAM with programmable secure or privilege or both areas.

• AHB and APB peripherals with programmable security and/or privileged access.


GTZC_NS
This section used to manage the Privileges in non-secure project for non-secure peripherals:

• TZSC (Security Controller):

This sub-block defines the privileged state of unsecured slave peripherals. It also controls the unprivileged area size for the watermark memory peripheral controller (MPCWM).
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