CORTEX

CORTEX_M7 The Cortex®-M7 core can execute high-performance tasks in parallel. The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and optimized power consumption, while delivering outstanding computational performance and low interrupt latency. The Cortex®-M7 processor is a highly efficient high-performance featuring: • Six-stage dual-issue pipeline • Dynamic branch prediction • Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache) • 64-bit AXI interface • 64-bit ITCM interface • 2x32-bit DTCM interfaces The following memory interfaces are supported: • Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency • Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM accesses • AXI Bus interface to optimize Burst transfers • Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. It also supports single and double precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. CORTEX_M7 The Cortex®-M7 core can execute high-performance tasks in parallel. The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and optimized power consumption, while delivering outstanding computational performance and low interrupt latency. The Cortex®-M7 processor is a highly efficient high-performance featuring: • Six-stage dual-issue pipeline • Dynamic branch prediction • Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache) • 64-bit AXI interface • 64-bit ITCM interface • 2x32-bit DTCM interfaces The following memory interfaces are supported: • Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency • Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM accesses • AXI Bus interface to optimize Burst transfers • Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. It also supports single and double precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation.