Arm Cortex-M0 low gate count, highly energy efficient
processor that is intended for microcontroller
and deeply embedded applications that require
an area optimized processor.]]> use in the lowest price chips. Key features of the Cortex-M0 core are:

- ARMv6-M architecture

- 3-stage pipeline.


Instruction sets:

- Thumb (most), missing CBZ, CBNZ, IT.

- Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR.

- 32-bit hardware multiply with 32-bit result.

- 1 to 32 interrupts, plus NMI.

]]> Arm Cortex-M0 + superset of the Cortex-M0. The Cortex-M0+
has complete instruction set compatibility
with the Cortex-M0 thus allowing the use of
the same compiler and debug tools.]]> power usage. In addition to debug features in the existing Cortex-M0, a silicon option
can be added to the Cortex-M0+ called the Micro Trace Buffer (MTB) which provides a simple
instruction trace buffer. The Cortex-M0+ also received Cortex-M3 and Cortex-M4 features, which
can be added as silicon options, such as the memory protection unit (MPU) and the vector table relocation.

Key features of the Cortex-M0+ core are:

- ARMv6-M architecture

- 2-stage pipeline (one fewer than Cortex-M0).

- Instruction sets: (same as Cortex-M0)

- Thumb (most), missing CBZ, CBNZ, IT.

- Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR.

- 32-bit hardware multiply with 32-bit result.

- 1 to 32 interrupts, plus NMI.

]]> Arm Cortex-M3 that features low gate count, low interrupt
latency, and low-cost debug. It is intended
for deeply embedded applications that require
optimal interrupt response features.]]> Key features of the Cortex-M3 core are:

- ARMv7-M architecture

- 3-stage pipeline with branch speculation.


Instruction sets:

- Thumb (entire).

- Thumb-2 (entire).

- 32-bit hardware multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply.

- 32-bit hardware divide (2-12 cycles).

- saturation arithmetic support.

- 1 to 240 interrupts, plus NMI.

- 12 cycle interrupt latency.

- Integrated sleep modes.

]]> Arm Cortex-M4 Cortex-M3 plus DSP Instructions, and a
floating-point unit (FPU).]]> Key features of the Cortex-M4 core are:

- ARMv7E-M architecture

- 3-stage pipeline with branch speculation.


Instruction sets:

- Thumb (entire).

- Thumb-2 (entire).

- 32-bit hardware multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply.

- 32-bit hardware divide (2-12 cycles).

- Saturation arithmetic support.

- DSP extension: Single cycle 16/32-bit MAC, single cycle dual 16-bit MAC, 8/16-bit SIMD arithmetic.

- 1 to 240 interrupts, plus NMI.

- 12 cycle interrupt latency.

- Integrated sleep modes.]]> Arm Cortex-M7 core with almost double the power
efficiency of the older Cortex-M4.
It features a 6-stage superscalar
pipeline with branch prediction and
an optional floating-point unit capable
of single-precision and optionally
double-precision operations. The
instruction and data buses have
been enlarged to 64-bit wide over
the previous
32-bit buses.]]> Key features of the Cortex-M7 core are:

- ARMv7E-M architecture.

- 6-stage pipeline with branch speculation.

Instruction sets:

- Thumb (entire).

- Thumb-2 (entire).

- 32-bit hardware multiply with 32-bit or 64-bit result,

- Signed or unsigned, add or subtract after the multiply.

- 32-bit hardware divide (2-12 cycles).

- Saturation arithmetic support.

- DSP extension: Single cycle 16/32-bit MAC, single cycle dual 16-bit MAC, 8/16-bit SIMD arithmetic.

- 1 to 240 interrupts, plus NMI.

- 12 cycle interrupt latency.

- Integrated sleep modes.

]]> Arm Cortex-M7 + Arm Cortex-M4 core with almost double the power
efficiency of the Cortex-M4, which is
conceptually a Cortex-M3 plus DSP Instructions
and a floating-point unit (FPU).
]]> Key features of the Cortex-M7 core are:

- ARMv7E-M architecture.

- 6-stage pipeline with branch speculation.

Cortex-M7 Instruction sets:

- Thumb (entire).

- Thumb-2 (entire).

- 32-bit hardware multiply with 32-bit or 64-bit result,

- Signed or unsigned, add or subtract after the multiply.

- 32-bit hardware divide (2-12 cycles).

- Saturation arithmetic support.

- DSP extension: Single cycle 16/32-bit MAC, single cycle dual 16-bit MAC, 8/16-bit SIMD arithmetic.

- 1 to 240 interrupts, plus NMI.

- 12 cycle interrupt latency.

- Integrated sleep modes.


Key features of the Cortex-M4 core are:

- ARMv7E-M architecture

- 3-stage pipeline with branch speculation.


Cortex-M4 Instruction sets:

- Thumb (entire).

- Thumb-2 (entire).

- 32-bit hardware multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply.

- 32-bit hardware divide (2-12 cycles).

- Saturation arithmetic support.

- DSP extension: Single cycle 16/32-bit MAC, single cycle dual 16-bit MAC, 8/16-bit SIMD arithmetic.

- 1 to 240 interrupts, plus NMI.

- 12 cycle interrupt latency.

- Integrated sleep modes.]]> Arm Cortex-A7 + Arm Cortex-M4 low-power processor.
The Cortex-M4 is conceptually a Cortex-M3
plus DSP Instructions and a floating-point unit (FPU).
]]> Key features of the Cortex-A7 MPcore are:

- ARMv7-A architecture

- 8-stage pipeline with branch speculation.

Cortex-A7 Instruction sets:

- 32-bit ARM instruction set.

- Thumb instruction set that has both 16-bit and 32-bit instructions.

- ThumbEE instruction set.

- Trivial implementation of the Jazelle Extension.

- Advanced SIMD and VFP Extensions.

- Security Extensions.

- Virtualization Extensions.

- Large Physical Address Extension.

- Multiprocessing Extensions.


Key features of the Cortex-M4 core are:

- ARMv7E-M architecture

- 3-stage pipeline with branch speculation.

Cortex-M4 Instruction sets:

- Thumb (entire).

- Thumb-2 (entire).

- 32-bit hardware multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply.

- 32-bit hardware divide (2-12 cycles).

- Saturation arithmetic support.

- DSP extension: Single cycle 16/32-bit MAC, single cycle dual 16-bit MAC, 8/16-bit SIMD arithmetic.

- 1 to 240 interrupts, plus NMI.

- 12 cycle interrupt latency.

- Integrated sleep modes.]]> Arm Cortex-M4 + Arm Cortex-M0+ plus DSP Instructions and a floating-point unit (FPU).
The Cortex-M0+ is an optimized
superset of the Cortex-M0. The Cortex-M0+
has complete instruction set compatibility
with the Cortex-M0 thus allowing the use of
the same compiler and debug tools.]]> Key features of the Cortex-M4 core are:

- ARMv7E-M architecture

- 3-stage pipeline with branch speculation.

Cortex-M4 Instruction sets:

- Thumb (entire).

- Thumb-2 (entire).

- 32-bit hardware multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply.

- 32-bit hardware divide (2-12 cycles).

- Saturation arithmetic support.

- DSP extension: Single cycle 16/32-bit MAC, single cycle dual 16-bit MAC, 8/16-bit SIMD arithmetic.

- 1 to 240 interrupts, plus NMI.

- 12 cycle interrupt latency.

- Integrated sleep modes.
Key features of the Cortex-M0+ core are:

- ARMv6-M architecture

- 2-stage pipeline (one fewer than Cortex-M0).

- Instruction sets: (same as Cortex-M0)

- Thumb (most), missing CBZ, CBNZ, IT.

- Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR.

- 32-bit hardware multiply with 32-bit result.

- 1 to 32 interrupts, plus NMI.

]]> Arm Cortex-M33 or digital signal control. TrustZone for Armv8-M is the foundation of security for all embedded applications.
The processor has many optional features including DSP, a co-processor interface, memory protection units and a floating-point unit.
The optional co-processor interface opens the door for customisation and extensibility to further decrease the power consumption of the system
in the presence of frequent compute intensive operations.
The Cortex-M33 achieves an optimal blend between real time determinism, energy efficiency, software productivity and system security
which opens the door for many new applications and opportunities across diverse markets.]]> Key features of the Cortex-M33 core are:

- Armv8-M Mainline (Harvard).

- 3-stage pipeline.

- Thumb/Thumb-2 ISA support.

- Optional Trustzone for Armv8-M

- Optional DSP/SIMD instructions.

- 3Single cycle 16/32-bit MAC.

- 8/16-bit SIMD arithmetic.

- Optional single precision floating point unit IEEE 754 compliant.

- Optional Memory Protection Unit (MPU) with up to 16 regions per security state.

- Optional dedicated co-processor bus interface for up to 8 co-processor units for custom compute.

- Non-maskable Interrupt (NMI) and up to 480 physical interrupts with 8 to 256 priority levels.

- Optional for waking up the processor from state retention power gating or when all clocks are stopped.]]> STM8 is implemented around a high-performance
8-bit core and a state-of-the-art set of peripherals.
This platform is manufactured using an ST-proprietary
130 nm embedded non-volatile memory technology.]]> It contains 6 internal registers, 20 addressing modes and 80 instructions.
The 6 internal registers include two 16-bit Index registers, an 8-bit Accumulator,
a 24-bit Program Counter, a 16-bit Stack Pointer and an 8-bit Condition Code register.
The two Index registers X and Y enable Indexed Addressing modes with or without offset,
along with read-modify-write type data manipulation. These registers simplify branching
routines and data/arrays modifications.

The STM8 platform supports four product series:

- STM8S, mainstream MCUs

- STM8L, ultra-low-power MCUs

- STM8AF and STM8AL, automotive MCUs

]]>