# Configuration file for the language: Verilog
# NOTE: This file is automatically generated by Enterprise Architect, changes made manually may be lost.
LEXER=verilog

# (Default)

# Brace Highlighting

# Caret Line

# Comments
COMMENT_LINECOMMENT_TOKEN=//~
COMMENT_STREAMCOMMENTSTART_TOKEN=/*
COMMENT_STREAMCOMMENTEND_TOKEN=*/

# Indentation

# Intellisense

# Language
KEYWORDS=always and assign begin xbuf buf bufif0 bufif1 case casex casez cmos default defparam else end endcase endfunction endmodule endprimitive endspecify endtable endtask event for force forever fork function if initial inout input integer join macromodule makefile module nand negedge nmos nor not notif0 notif1 or output parameter pmos posedge primitive pulldown pullup rcmos real realtime reg repeat rnmos rpmos rtran rtranif0 rtranif1 signed specify specparam supply supply0 supply1 table task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg vectored wait wand while wire wor xnor xor
TASKS=$readmemb $readmemh $sreadmemb $sreadmemh $display $write $strobe $monitor $fdisplay $fwrite $fstrobe $fmonitor $fopen $fclose $time $stime $realtime $scale $printtimescale $timeformat $stop $finish $save $incsave $restart $input $log $nolog $key $nokey $scope $showscopes $showscopes $showvars $showvars $countdrivers $list $monitoron $monitoroff $dumpon $dumpoff $dumpfile $dumplimit $dumpflush $dumpvars $dumpall $reset $reset $reset $reset $reset $random $getpattern $rtoi $itor $realtobits $bitstoreal $setup $hold $setuphold $period $width $skew $recovery

# Literals
WORD_CHARACTERS=abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789_`$#

# Macros

# Preprocessor

# Whitespace
